A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCl). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption

There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory blocks are performed.

There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory bocks are performed.

An erasing method of a nonvolatile semiconductor memory device of the disclosure includes erasing data of a selected memory cell (step S100); immediately applying a programming voltage lower than a programming voltage in a programming time to all control gates of the selected memory cell after the erasing step, thereby performing a week programming (step S110); performing a erasing verification of the selected memory cell (step S120).

A programming method for a PMOS multi-time programmable (MTP) flash memory device biases the select gate transistor to a constant drain current level and sweeps the control gate bias voltage from a low voltage level to a high voltage level while maintaining the cell current around a predetermined cell current limit level. In this manner, the PMOS MTP flash memory device can achieve low power and high speed program using hot carrier injection (HCI). The programming method of the present invention enables multi-bit programming of the PMOS MTP flash memory cells, thereby increasing the programming speed while preserving low power consumption.

A method of controlling a nonvolatile memory device, includes: determining, based on a write address, whether selected memory cells of the nonvolatile memory device corresponding to the write address are included in an over-erased group; based on the selected memory cells being included in the over-erased group, performing a preprogram operation to increase threshold voltages of an over-erased state of the selected memory cells; and after completion of the preprogram operation, performing a data program operation to store write data in the selected memory cells.

A controller of a memory device may determine that an endurance parameter associated with a wear leveling pool of a memory of the memory device satisfies a threshold. The wear leveling pool includes a plurality of memory blocks of the memory. The controller may divide, based on determining that the endurance parameter satisfies the threshold, the plurality of memory blocks of the wear leveling pool into a first wear leveling pool subset that includes a first subset of the plurality of memory blocks and a second wear leveling pool subset that includes a second subset of the plurality of memory blocks. A first subset of a plurality of data partitions is stored in the first subset of the plurality of memory blocks, and a second subset of the plurality of data partitions is stored in the second subset of the plurality of memory blocks.