A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

A memory device may include: a control circuit comprising a first verification component suitable for counting the number of memory cells in the selected word line having an excessively high threshold voltage as excessive memory cells, after a program operation is completed; and a second verification component suitable for counting the number of failed bits when the number of excessive memory cells counted is greater than or equal to an excess threshold value, and suitable for outputting a pass or fail signal for the program operation according to the count of at least one of the first verification component and the second verification component.

A memory system includes a nonvolatile memory device including a plurality of memory cells; and a controller including a control unit and a random-access memory, and configured to determine, by applying a program verify voltage to at least one memory cell to be programmed with program data, whether the program data is programmed, wherein the control unit determines percentages of a count of read requests received from a host device and a count of program requests received from the host device, and adjusts a level of the program verify voltage based on the percentages.

A method of managing programming errors in a multilevel NAND flash memory is provided. The multilevel NAND flash memory uses a two-pass programming algorithme.g., a first programming pass and a second programming passfor programming a memory block being organized in pages, sharing a word line. The method comprises performing the first programming pass for at least one memory page, reading the at least one memory page between the first programming pass and the second programming pass, determining an error count value for the at least one programmed memory page, and responsive to determining that the error count value is below a threshold value, performing the second programming pass with active data.

An embodiment of a semiconductor package apparatus may include technology to attempt to program data in a first portion of a nonvolatile memory, determine if the attempt was successful, and recover the data to a second portion of the nonvolatile memory with an internal data move operation if the attempt is determined to be not successful. Other embodiments are disclosed and claimed.

In a memory device having improved reliability, the memory device includes: a memory cell array including memory cells; a program operation controller configured to perform a program operation on the memory cells to any one state among first to nth states; a voltage generator configured to generate operating voltages respectively corresponding to the first to nth states in the program operation; a verify operation controller configured to verify whether the program operation performed on selected memory cells to a kth state, has been completed, and count a number of over-programmed memory cells having a threshold voltage greater than a threshold voltage corresponding to the kth state among the selected memory cells; and an over-program manager configured to increase operating voltages corresponding to (k+1)th to nth states to be greater than default values according to the number of over-programmed memory cells.

A memory controller executes a non-homogeneous bitline biasing program verify operation on bitlines of a memory array, and a homogeneous bitline biasing program verify operation on the bitlines. A count of bitlines responding in a particular way to each type of biasing is used to ascertain the integrity of the memory array.

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.