A semiconductor memory device and a method of operating the same are provided. The method of operating the semiconductor memory device includes determining a target word line coupled to an over-programmed memory cell, backing up data stored in memory cells coupled to the target word line in a second memory area, wherein the se second memory area is different from a first memory area where the memory cells coupled to the target word line are disposed, and applying a stepped-up read pass voltage to the target word line when a read operation is performed on a selected memory cell in a memory block coupled to the target word line, wherein the selected memory cell is different from the over-programmed memory cell. Therefore, the operation reliability of the semiconductor memory device is improved.

A memory system comprising: a nonvolatile memory device including a plurality of pages, and suitable for performing one among a first program operation of performing program and verify operations according to an incremental step pulse programming (ISPP) scheme and a second program operation of first performing a verify operation and then performing program and verify operations according to the ISPP scheme when the program operation is to be performed to each of the plurality of pages; and a controller suitable for controlling the nonvolatile memory device to perform the second program operation when a target page meets an operation condition of a reprogram, and to perform the first program operation when the target page does not meet the operation condition of the reprogram.

Numerous embodiments are provided for compensating for drift error in non-volatile memory cells within a VMM array in an analog neuromorphic memory system. For example, in one embodiment, a circuit is provided for compensating for drift error during a read operation, the circuit comprising a data drift monitoring circuit coupled to the array for generating an output indicative of data drift; and a bitline compensation circuit for generating a compensation current in response to the output from the data drift monitoring circuit and injecting the compensation current into one or more bitlines of the array.

Methods, systems, and machine-readable storage medium for programming a storage device are disclosed. In some embodiments, the methods include: performing a verify operation on a plurality of storage elements of the storage device to determine whether the plurality of storage elements have been programmed to a first program state; determining a first number of failing bits corresponding to the first program state based on the verify operation; comparing the first number of failing bits with a first threshold of failing bits corresponding to the first program state; and determining a second threshold of failing bits based at least in part on the first number of failing bits and the comparison, wherein the second threshold of failing bits corresponds to a second program state.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

Methods of operating a memory device include programming a page of a memory block of the memory device using a particular starting programming voltage, determining a programming voltage indicative of a programming efficiency of the page of the memory block during programming of the page of the memory block, storing a representation of the programming voltage indicative of the programming efficiency of the page of the memory block, setting a starting programming voltage for a different page of the memory block in response to the stored representation of the programming voltage indicative of the programming efficiency of the page of the memory block, and programming the different page of the memory block using its starting programming voltage.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.

The memory device includes a plurality of memory cells that are arranged in word lines, including a selected word line. Circuitry is configured to program at least some of the plurality of memory cells of the selected word line in at least one program loop of a programming operation. During the at least one program loop, the circuitry is configured to apply a programming pulse to the selected word line, perform a verify operation, and perform an analog bitscan operation. The circuitry is further configured to determine an output of the analog bitscan operation, the output being one of at least three options. The circuitry is also configured to control at least one programming parameter based on the output of the analog bitscan operation. The at least one programming parameter is an early program-verify termination parameter or a smart verify parameter.

A nonvolatile semiconductor memory device includes a control circuit configured to control a soft program operation of setting nonvolatile memory cells to a first threshold voltage distribution state of the nonvolatile memory cells. When a characteristic of the nonvolatile memory cells is in a first state, the control circuit executes the soft program operation by applying a first voltage for setting the nonvolatile memory cells to the first threshold voltage distribution state to first word lines, and applying a second voltage higher than the first voltage to a second word line. When the characteristic of the nonvolatile memory cells is in a second state, the control circuit executes the soft program operation by applying a third voltage equal to or lower than the first voltage to the first word lines and applying a fourth voltage lower than the second voltage to the second word line.