According to a certain embodiment, the semiconductor memory device includes a memory cell array, a control circuit, and a data register storing an erase verify fail flag. An erase target block is divided into word line groups. The control circuit includes: a counter configured to count the number of the erase verify fail flags to be output as a count value for each group; a plurality of counter registers configured to store the count value for each group; an arithmetic circuit configured to take a difference of the plurality of count values respectively stored in the plurality of counter registers and to output a result of the difference as a number of second fail flags; and a comparator configured to compare the number of criteria of the erase verify fail flag and the number of the second fail flags to be output as a memory state detected result.

A memory device includes a memory string and a control circuit coupled to the memory string. The memory string includes a top select gate, word lines, a bottom select gate, and a P-well. The control circuit is configured to, in an erasing operation, apply an erasing voltage to the P-well, apply a verifying voltage to a selected word line of the word lines after applying the erasing voltage to the P-well, and apply a first turn-on voltage to the bottom select gate, starting after applying the erasing voltage to the P-well and before applying the verifying voltage to the selected word line.

An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

A processing device sets a first flag that indicates whether a first critical security parameter (CSP) file exists. The first CSP file includes a first set of CSPs for a memory device. The processing device sets a second flag that indicates whether the first CSP file is valid. The processing device sets a third flag that indicates whether a second CSP file exists. The second CSP file includes a second set of CSPs for the memory device. The processing device sets a fourth flag that indicates whether the second critical security parameter file is valid. The processing device selects one of the first or second CSP file as an active CSP file based on an evaluation of the first, second, third, and fourth flags.

A nonvolatile memory device includes a memory cell array, an erase body voltage generator, and an erase source voltage generator. The memory cell array includes memory blocks, each of which includes cell strings each including a ground selection transistor, memory cells, and a string selection transistor stacked in a direction perpendicular to a substrate. The erase body voltage generator applies an erase body voltage to the substrate during an erase operation. The erase source voltage generator applies an erase source voltage to a common source line connected with ground selection transistors of the cell strings during the erase operation.

Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.

A method of verifying the programming of a plurality of memory cells in a data storage system includes performing a setup operation including settling of bit lines associated with the subset of memory cells; performing a sensing operation including subjecting the settled bit lines to a verify voltage signal; and performing first and second latching operations identifying memory cells of the subset of memory cells having threshold voltages that meet first and second verify reference voltages, where the first and second latching operations are part of the same program verify operation with no setup time between them.

The present disclosure relates to a method for improving the safety of the reading phase of a non-volatile memory device including at least an array of memory cells and with associated decoding and sensing circuitry and a memory controller, the method comprising: storing in a dummy row of said memory block at least a known pattern; performing some reading cycles changing the read trimming parameters up to the moment wherein said known value is read correctly; adopting the trimming parameters of the correct reading for the subsequent reading phases. The disclosure further relates to a memory device structured for implementing the above method.

An erasing method is used in a memory device. The memory device includes a string of memory cells and a controller, the string of memory cells including a plurality of special memory cells not for storing data and a plurality of main memory cells for storing data. The erasing method includes: the controller verifying if at least one special memory cell of the plurality of special memory cells has failed; the controller resetting the at least one special memory cell if the at least one special memory cell has failed; and the controller erasing the plurality of main memory cells.

A semiconductor storage device includes a plurality of planes, the planes including a first plane and a second plane, an interface circuit configured to receive and transmit control signals for the planes, and a control circuit configured to control the planes based on the control signals. While a first operation that includes multiple loops of a high voltage operation and a verify operation is being performed by the first plane, the control circuit controls the second plane to perform a second operation during at least one period in which the verify operation is performed by the first plane.