The present technology relates to a memory device and a method of operating the same. The memory device includes a memory block including a plurality of strings, a peripheral circuit configured to perform an erase operation including a first erase operation, an erase verify operation, and a second erase operation on the memory block, and a control logic configured to control the peripheral circuit to perform the erase operation. During the second erase operation, the control logic controls the peripheral circuit to apply a first erase voltage to a source line of the memory block and apply a second erase voltage, which is lower than the first erase voltage, to a bit line connected to a string determined as erase pass among the plurality of strings.

The invention provides a storage structure and an erase method thereof, capable of performing an erase operation on a plurality of memory blocks. The storage structure includes: a first storage body, a second storage body, a third storage body, and a controller. Memory blocks that are consecutively numbered are sequentially alternately stored in the first memory bank, the second memory bank, and the third memory bank, and the controller is configured to control each memory block to sequentially undergo a first process, a second process and a third process. The erase method includes: when a memory block Bi undergoes the third process, a memory block Bi+1 undergoes the second process, and a memory block Bi+2 undergoes the first process at the same time; where i ∈ [1, n−2]. Three adjacent blocks undergo the first process, the second process, and the third process simultaneously.

A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.

Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.

An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.

The present technology relates to an electronic device. According to an embodiment of the present disclosure, a memory device may include a plurality of memory cells connected to each word line, a peripheral circuit configured to perform a program operation on memory cells that are connected to a selected word line, and a control logic configured to control the peripheral circuit to perform the program operation on the memory cells that are connected to the selected word line after performing a pre-program operation that increases a threshold voltage of over-erasure cells, among memory cells that are connected to an adjacent word line, having a threshold voltage of an over-erasure state that is lower than a threshold voltage of an erasure state, to the threshold voltage of the erasure state, wherein the adjacent word line is a word line that is next to the selected word line.

A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

A memory device includes an erase operation controller for performing an erase operation on a memory block; an erase suspend count manager for managing an erase suspend count representing a number of times the erase operation is suspended until the erase operation on the memory block is completed; and a program parameter value determiner for determining a parameter value to be used for a program operation on the memory block, based on the erase suspend count.

A method of operating a storage system is provided. The storage system includes memory cells and a memory controller, wherein each memory cell is an m-bit multi-level cell (MLC), where m is an integer, and the memory cells are arranged in m pages. The method includes determining initial LLR (log likelihood ratio) values for each of the m pages, comparing bit error rates in the m pages, identifying a programmed state in one of the m pages that has a high bit error rate (BER), and selecting an assist-read threshold voltage of the identified page. The method also includes performing an assist-read operation on the identified page using the assist-read threshold voltage, determining revised LLR values for the identified page based on results from the assist-read operation, and performing soft decoding using the revised LLR values for the identified page and the initial LLR values for other pages.

An example method includes, performing a first erase verify on a first set of memory cells of a portion of an array of memory cells, performing a second erase verify on a second set of memory cells of the portion of the array, applying a first erase voltage pulse concurrently to each memory cell in the portion of the array if the first set fails the first erase verify and if the second set fails the second erase verify, and applying a second erase voltage pulse concurrently to each memory cell in the portion of the array if the first set passes the first erase verify and if the second set fails the second erase verify. The second erase voltage pulse is different than the first erase voltage pulse.