A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading a first physical unit based on a first read voltage level to obtain first data; reading the first physical unit based on a second read voltage level to obtain second data; reading the first physical unit based on a third read voltage level to obtain third data; obtaining a first reference value which reflects a data variation status between the first data and the second data; obtaining a second reference value which reflects a data variation status between the first data and the third data; reading the first physical unit based on a fourth read voltage level to obtain fourth data according to the first reference value and the second reference value; and decoding the fourth data by a decoding circuit.

A memory device includes: a memory cell array including a plurality of memory blocks; peripheral circuits for performing a program operation on a selected memory block among the plurality of memory blocks and programming memory cells that are included in the selected memory block to a plurality of program states during the program operation; and a control logic for controlling the peripheral circuits to perform the program operation. The control logic counts a program pulse number that is used during the program operation and determines whether the selected memory block is a bad block, based on the counted program pulse number.

An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.

When programming and verifying a memory device which includes a plurality of memory cells and a plurality of word lines, a first coarse programming is first performed on a first memory cell among the plurality of memory cells which is controlled by a first word line among the plurality of word lines, and then a second coarse programming is performed on a second memory cell among the plurality of memory cells which is controlled by a second word line among the plurality of word lines. Next, a first coarse verify current is used for determining whether the first memory cell passes a coarse verification and a second coarse verify current is used for determining whether the second memory cell passes a second coarse verification, wherein the second coarse verify current is smaller than the first coarse verify current.

According to one embodiment, a memory device includes a memory cell, a word line connected to the memory cell, a word line driver which generates a selection signal for the word line, a first transistor including a gate to which the selection signal generated by the word line driver is input, and a drain which supplies a signal based on the selection signal to the word line, and a detection circuit which detects a value based on a current flowing through the first transistor during a verification period after writing data to the memory cell.

A memory device includes a page with plurality of memory cells and a peripheral circuit that performs at least one program loop. The at least one program loop includes a program voltage applying phase for applying, during a program operation, a program voltage to a word line to which the plurality of memory cells are coupled and a program verify phase for determining whether a selected memory cell among the plurality of memory cells has been completely programmed. The memory device includes control logic that controls the peripheral circuit to: perform an auxiliary verify operation of applying an auxiliary verify voltage to the word line; perform a main verify operation of applying a main verify voltage larger than the auxiliary verify voltage to the word line; and determine a fail of the program operation, based on verify data obtained by performing the auxiliary verify operation and the main verify operation.

According to one embodiment, a semiconductor memory device includes: a first bit line; a first memory cell electrically coupled to the first bit line; and a first sense amplifier configured to sense and store data read out to the first bit line. The first sense amplifier includes a first latch circuit and a second latch circuit. In a program operation, each of the first and second latch circuits stores any one bit of program data. In a first verify operation, data is exchanged between the first latch circuit and the second latch circuit when performing the first verify operation for a first data.

A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.

An operating method of a non-volatile memory device including a plurality of memory cells respectively connected to a plurality of word lines is provided. The operating method includes applying an erase detect voltage to a selected word line of the plurality of word lines to perform an erase detect operation on memory cells connected to the selected word line in response to a program command, applying a program voltage to the selected word line after the erase detect operation, and counting a number of undererased cells of the memory cells on which the erase detect operation has been performed.

A nonvolatile memory device includes a peripheral circuit region and a memory cell region vertically connected with the peripheral circuit region, the peripheral circuit region including at least one first metal pad, and the memory cell region including at least one second metal pad directly connected with the at least one first metal pad. A method of programming the nonvolatile memory device includes: receiving a programming command, data for a plurality of pages, and an address corresponding to a selected word-line; programming the data for one of the pages to an unselected word-line; reading data of a previously programmed page from the selected word-line; and programming the data for the remaining pages and the data of the previously programmed page to the selected word-line.