The present disclosure relates to circuit structures and, more particularly, to circuit structures which detect high speed and high precision characterization of VTsat and VTlin of FET arrays and methods of manufacture and use. The circuit includes a control loop comprised of a differential amplifier, a plurality of FET arrays, and at least one analog switch enabling selection between a calibration mode and an operation mode.

A memory calibration method and system and a vehicle system are disclosed. The method includes reading a first set of data from a first memory, wherein the first set of data includes pre-stored parameters for calibrating a second memory comprising a controller; performing a first verification process on the first set of data; performing a second verification process on the first set of data when the first set of data passes the first verification process; adopting the first set of data to configure the controller of the second memory when the first set of data passes the second verification process; and performing a test for the second memory to determine whether finishing a current calibration process for the second memory, wherein the second memory has been calibrated when the second memory passes the test.

In various embodiments, a memory module houses memory devices and, in some embodiments, a memory controller. Each of the devices has a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on, for example, a memory device substrate or molded into a plastic mold to create near-field magnetic coupling between the stacked memory devices and, in certain embodiments, the memory controller. Other embodiments are disclosed.

In various embodiments, a memory module houses memory devices and, in some embodiments, a memory controller. Each of the devices has a near-field interface coupled to loop antennas to communicate over-the-air data. A coil is formed on, for example, a memory device substrate or molded into a plastic mold to create near-field magnetic coupling between the stacked memory devices and, in certain embodiments, the memory controller. Other embodiments are disclosed.

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

A flash memory comprising a first plurality of memory cells, each memory cell of the first plurality of memory cells selectively connected to a first input of a comparator. A second plurality of memory cells selectively connected to a second input of the comparator, wherein a first number of the second plurality of memory cells are in an erased state, wherein a second number of the second plurality of memory cells are in a written state, wherein each memory cell of the first plurality of memory cells and each memory cell of the second plurality of memory cells has a first cell capacitance, and wherein the sum of the first number and the second number is at least three.

A semiconductor memory device including a pair of first bit lines extended in a first direction, a pair of second bit lines extended in the first direction, a first word line extended in a second direction crossing the first direction, a second word line extended in the second direction, a memory cell surrounded by the first bit line, the second bit line, the first word line, and the second word line, and including a drive transistor, a first transfer transistor coupled with one of the pair of first bit lines, and having a gate coupled with the first word line, a second transfer transistor coupled with one of the pair of second bit lines, and having a gate coupled with the second word line, and a load transistor, a write drive circuit that transfers data to the memory cell.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

A gate driving circuit and a display panel with the gate driving circuit are provided. The gate driving circuit includes shift registers for providing scan signals to gate lines of the display panel. Each shift register includes a main circuit and a discharge circuit. In the main circuit, a pre-charge unit is coupled to a first node and is configured to output a pre-charge signal to the first node, a pull-up unit is coupled to the first node and a second node and is configured to output an m.sup.th stage scan signal of the 1.sup.st to N.sup.th stage scan signals to the second node; and a reset unit is coupled to the first node and is configured to receive a reset signal. In the discharge circuit, a pull-down unit is coupled to the first node and the second node and is configured to receive a pull-down control signal.