A method for migrating data to avoid read disturbance is introduced to contain the following steps: obtaining first read counts corresponding to physical blocks from a first read-count table; obtaining second read counts corresponding to the physical blocks from a second read-count table; subtracting each first read count from one corresponding second read count to generate third read counts; finding a singular physical-block from physical blocks according to the third read counts; performing a test read on data of the i.sup.th physical page of the singular physical-block; determining whether the data of the i.sup.th physical page of the singular physical block has passed the test read; and if so, moving or copying data of the i.sup.th physical page and at least one neighboring physical-page of the singular physical block to an available physical-block.

Memory devices may provide a communication interface that is configured to receive control signals, and/or address signals from user circuitry, such as a processor. The memory device may receive and process signals employing different signal paths that may have different latencies, leading to clock skews. Embodiments discussed herein the application are related to interface circuitry that may decrease certain response times of the memory device by adding delays that minimize the clock skews. For example, a delay in a control path, such as a chip select path, may allow reduction in a delay of an address path, and leading to a decrease of the access time of the memory device. Embodiments also disclose how training modes may be employed to further adjust the delays in the control and/or address paths to decrease access times during regular operation.

A test method for a semiconductor memory device having a plurality of memory cells arranged in a matrix form, the test method including writing first data into a plurality of memory cells, while a plurality of word lines disposed in the columns of the memory cells are deselected, driving the low-potential side bit line of a bit line pair in the selected column, which is among a plurality of bit line pairs disposed in the columns of the memory cells, to a negative voltage level in accordance with second data complementary to the first data, and reading the data written into the memory cells.

A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

A memory system and method of operating the same is described, where the memory system is used to store data in a RAIDed manner. The stored data may be retrieved, including the parity data so that the stored data is recovered when the first of either the stored data without the parity data, or the stored data from all but one memory module and the parity data, has been received. The writing of data, for low write data loads, is managed such that only one of the memory modules of a RAID stripe is being written to, or erased, during a time interval.

A method for migrating data to avoid read disturbance is introduced to contain the following steps: obtaining first read counts corresponding to physical blocks from a first read-count table; obtaining second read counts corresponding to the physical blocks from a second read-count table; subtracting each first read count from one corresponding second read count to generate third read counts; finding a singular physical-block from physical blocks according to the third read counts; performing a test read on data of the i.sup.th physical page of the singular physical-block; determining whether the data of the i.sup.th physical page of the singular physical block has passed the test read; and if so, moving or copying data of the i.sup.th physical page and at least one neighboring physical-page of the singular physical block to an available physical-block.

A method includes: examining, by a test engine, whether a first bit of a memory array is functional; in response to the first bit being not functional, storing, by the test engine, address information of the first bit into a memory device; and retrieving, by an assist circuit trimming (ACT) circuit, the address information of the first bit from the memory device to selectively activate at least a first one of a plurality of assist circuits associated with the first bit.

The semiconductor memory device includes a cell array unit comprising a plurality of cell mats; a column decoder suitable for outputting a plurality of column selection signals based on a column address to a plurality of column selection lines, respectively, during a normal operation, and for applying a signal having a first logic level to the plurality of column selection lines during a test operation; and a line defect detection circuit suitable for detecting whether a defect is present in the plurality of column selection lines in response to signals of the plurality of column selection lines, and outputting a defect detection signal based on the detection result, during the test operation.