Provided is a semiconductor memory device that is capable of accurately detecting a retention failure of a memory cell. The semiconductor memory device includes a memory array including a plurality of memory cells arranged in a matrix form, a plurality of bit line pairs disposed in the columns of the memory cells, a plurality of word lines disposed in the rows of the memory cells, a write drive circuit adapted to transfer data to a bit line pair in a selected column in accordance with write data, and a control circuit that deselects the word lines during a test and drives a low-potential side bit line of the bit line pair in the selected column to a negative voltage level in accordance with the potentials of bit lines in the selected column.

A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.

A memory device comprising a memory array comprising a plurality of memory cells, two or more fuses coupled to the memory array, wherein each of the two or more fuses contains trim data for the memory array and a mode register for selecting one of the two or more fuses to be enabled.

Systems and methods for low latency acquisition of soft data from a memory cell based on a sensing time and/or a leakage current are described. In one embodiment, the systems and methods may include applying a first read voltage to a word line of a page of memory cells selected by a processor of a flash memory device for a read operation, applying a pass voltage to word lines associated with one or more different pages of memory cells of the memory block, upon applying the first read voltage sensing whether a bit line of a memory cell in the selected page conducts, measuring a side effect associated with sensing whether the bit line of the memory cell in the selected page conducts, and assigning a LLR value to the memory cell as a soft LDPC input based at least in part on the measured side effect.

The present disclosure provides circuit and method embodiments for calibrating a signal of an integrated circuit. A programmable resistive element is coupled in series with a node of the integrated circuit, where at least part of the integrated circuit is formed in at least one front end of line (FEOL) device level. The programmable resistive element is formed in at least one back end of line (BEOL) wiring level, and the programmable resistive element is in a non-volatile resistive state that is variable across a plurality of non-volatile resistive states in response to a program signal applied to the programmable resistive element.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

The present disclosure includes apparatuses and methods for parallel writing to multiple memory device locations. An example apparatus comprises a memory device. The memory device includes an array of memory cells and sensing circuitry coupled to the array. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A memory controller in the memory device is configured to receive a block of resolved instructions and/or constant data from the host. The memory controller is configured to write the resolved instructions and/or constant data in parallel to a plurality of locations the memory device.

An interface circuit includes multiple signal processing devices and a monitor and calibration module including multiple monitoring circuits, multiple calibration circuits and a compensation control mechanism operation logic. The monitoring circuits monitor a reception signal, a transmission signal, a power supplying voltage and a ground voltage to correspondingly generate monitored results. The calibration circuits perform a calibration operation on at least one signal processing device to adjust a characteristic value of the signal processing device. The compensation control mechanism operation logic generates a calibration control signal to control the calibration operation of the calibration circuits based on the monitored results. The compensation control mechanism operation logic is implemented by FPGA and includes a calibration handle interface which generates the calibration control signal according to a decoding result of a calibration command and transmits the calibration control signal to one of the calibration circuits.