A tool for performing a logic built-in self-test of an electronic circuit operating on a clock cycle basis. The tool stores a configurable test signature in a random-access memory together with a pattern counter for a test pattern, wherein a number of the at least one additional signature register corresponds to a number of entries in the random access memory. The tool determines an error based, at least in part, on a compare operation for a given test pattern, wherein the compare operation determines whether the test signature in the first signature register before a capture cycle of a next test pattern differs from the corresponding configurable test signature. The tool stores the error in a corresponding additional signature register.

A system comprises a memory sub-system controller mounted to a printed circuit board (PCB) and an in-circuit test (ICT) device. The memory sub-system controller has test points on the PCB comprising stimulus points and observation points. The ICT device connects to the test points of the controller. The ICT device converts automated test pattern generation (ATPG) input test vectors to test signals. A first set of pin drivers of the ICT device applies the test signals to the stimulus points of the controller and a second set of pin drivers of the ICT device read output signals output at the observation points of the controller. A comparator of the ICT device compares the output signals with output test vectors. The comparator provides test result data comprising a result of the comparison.

The present disclosure relates to a static random-access memory and an electronic device. The memory includes at least one storage circuit, wherein the storage circuit includes a first inverter, a second inverter, a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a word-line, a first bit-line, a second bit-line, a shift-input line, and a shift-output line. The circuit is used to access data by using the first bit-line and/or the second bit-line when it works in a first mode, and the circuit is used to shift the input data to the shift-input line and output the shifted data through the shift-output line when it works in a second mode. By implementing shift-input and shift-output within the memory, the disclosed embodiment can achieve high-concurrency data access and data update, and it also enables high integration and low power consumption.

A 3D semiconductor device with a built-in-test-circuit (BIST), the device comprising: a first single-crystal substrate with a plurality of logic circuits disposed therein, wherein said first single-crystal substrate comprises a device area, wherein said plurality of logic circuits comprise at least a first interconnected array of processor logic, wherein said plurality of logic circuits comprise at least a second interconnected set of circuits comprising a first logic circuit, a second logic circuit, and a third logic circuit, wherein said second interconnected set of logic circuits further comprise switching circuits that support replacing said first logic circuit and/or said second logic circuit with said third logic circuit; and said built-in-test-circuit (BIST), wherein said first logic circuit is testable by said built-in-test-circuit (BIST), and wherein said second logic circuit is testable by said built-in-test-circuit (BIST).

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

The present invention is related to a digital circuit testing and analysis module system comprising a memory (22). The memory (22) is addressed by numerical values defined by a group of digital signals. A respective memory location associated with a specific numerical value indicates a status of the group of digital signals. The status can for example reflect the validity of the signals in the group of signals when testing a circuit.

The present disclosure relates to an apparatus comprising a host device and a memory component coupled to the host device. The memory component can comprise an array of memory cells, and an interface comprising a boundary scan architecture, wherein the boundary scan architecture includes an instruction register configured to store data indicative of a presence of a test data input (TDI) signal.

Provided is a memory macro which allows detection of a fault in a fetch circuit for an address signal which is input. The memory micro includes an address input terminal, a clock input terminal, a memory array and a control unit. The control unit includes a temporary memory circuit which fetches an input address signal which is input into the address input terminal in synchronization with an input clock signal which is input from the clock input terminal and outputs the input address signal as an internal address signal. The memory macro further includes an internal address output terminal which outputs the internal address signal for comparison with the input address signal.

A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.

A test circuit for testing a semiconductor device including semiconductor chips, includes: a test input terminal configured to receive data for testing the semiconductor device; signal paths provided between one semiconductor chip in the semiconductor chips and another semiconductor chip in the semiconductor chips, data supplied to the test input terminal being transmitted through the signal paths; a select signal generator, provided in the one semiconductor chip and coupled to the another semiconductor chip via the signal paths, configured to generate, when receiving data indicating expected values via one or more signal paths in the signal paths, a select signal indicating the one or more signal paths; and a path selector, provided in the at least one semiconductor chip and coupled to the signal paths, configured to select, based on the select signal, signal paths to be used at the time of testing the semiconductor device.