The disclosure relates to a system and method for maintaining stability during a scan shift operation on multiple embedded memories in an integrated circuit. Examples disclosed herein include an integrated circuit comprising a plurality of memory modules and a built-in self-test controller, wherein the BIST controller and memory modules are arranged and configured to reduce toggling of cells in the memory modules during a scan shift operation.

An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

An example memory device with an improved sensing structure including a memory array comprising a plurality of sub-arrays of memory cells and structured in memory blocks, sense amplifiers coupled to the memory cells, and modified JTAG cells coupled in parallel to the outputs of the sense amplifiers and serially interconnected in a scan-chain structure integrating a JTAG structure and the sense amplifiers. In the example memory device, the scan-chain structures associated to each sub array are interconnected to form a unique chain as a boundary scan register. Further, in the example memory device, the boundary scan register is a testing structure to test interconnections of the sense amplifiers.

A test circuit for testing a memory is provided. The input of the memory is coupled to a register, and the register is coupled to a logic circuit. The test circuit includes a first test register group, a second test register group, a first multiplexer, and multiple second multiplexers. The first test register group includes at least one test register. The second test register group includes at least one test register. The first multiplexer is coupled between the first test register group and the register. The second multiplexers are coupled between the second test register group and the register.

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

The present disclosure relates to an apparatus, and a method for memory management and more a memory device structured with internal analogic measurement mode features. The memory device includes memory component having a memory array, a memory controller coupled to the memory component, a JTAG interface in the memory controller, voltage and current reference generators, and an analogic measurement block driven by the JTAG interface.

Boundary test circuit, memory and boundary test method are provided. The boundary test circuit may include a plurality of serially-connected wrapper boundary registers (WBRs) and a plurality of toggle circuits (TCs). Each WBR may include a first I/O for receiving an initial test signal and a second I/O for transmitting the initial test signal to the WBR at a succeeding stage. Each TC may include an input for receiving the initial test signal stored in a corresponding WBR, a control I/O for receiving a toggle signal, and an output for transmitting a real-time test signal to the integrated circuit. The toggle signal may be configured to control phase switching of the real-time test signal, and, depending on the toggle signal, the real-time test signal may have a phase identical or inverse to a phase of the initial test signal. This method improves the efficiency and flexibility of the boundary test.

A decoder decodes a memory address and selectively drives a select line (such as a word line or mux line) of a memory. An encoding circuit encodes the data on select lines to generate an encoded address. The encoded address and the memory address are compared by a comparison circuit to generate a test result signal which is indicative of whether the decoder is operating properly. To test the comparison circuit for proper operation, a subset of an MBIST scan routine causes the encoded address to be blocked from the comparison circuit and a force signal to be applied in its place. A test signal from the scan routine and the force signal are then compared by the comparison circuit, with the test result signal generated from the comparison being indicative of whether the comparison circuit itself is operating properly.