Provided is an integrated circuit that includes a reset electrically connected to a select line of a multiplexer and an OR gate. The multiplexer receives data from a power source. The multiplexer and the OR gate comprise a circuit. A clock is electrically connected to the OR gate. The OR gate is electrically connected to a clock input of a latch. The latch includes the clock input, a scan enable input, a data input, and a data output. A regular logic data path is electrically connected to the multiplexer, and the multiplexer is further electrically connected to the data port of the latch.

A memory tester of the present embodiment includes a first memory, a second memory, an arithmetic circuit, and a determination circuit. The first memory is configured to store scan input data and expected value data, the scan input data including a don't care bit, the expected value data being obtained by converting the don't care bit into a first predetermined value. The second memory is configured to store scan output data and mask data obtained by converting a value of the scan input data other than the don't care bit into a second predetermined value. The arithmetic circuit is configured to perform an exclusive or operation between the expected value data and the scan output data. The determination circuit is configured to determine whether the don't care bit of an arithmetic result from the arithmetic circuit is passed or failed by using the mask data.

The present invention discloses a memory test circuit having repair information maintaining mechanism. A repairing control circuit controls a MBISR circuit to perform a self-repair procedure on a memory circuit and includes a remapping storage circuit and a latch storage circuit. The remapping storage circuit receives and stores repairing information generated by the MBISR circuit after the self-repair procedure finishes. The latch storage circuit is electrically coupled between the remapping storage circuit and a remapping circuit corresponding to the memory circuit to receive and store the repairing information from the remapping storage circuit such that the remapping circuit accesses the repairing information therefrom when a scan test is performed on the remapping storage circuit based on a scan chain to perform remapping and repairing on the memory circuit based on the repairing information and a redundant structure of the memory circuit.

A memory is provided in which a scan chain covers the redundancy logic for column redundancy as well as the redundancy multiplexers in each column. The redundancy logic includes a plurality of redundancy logic circuits arranged in series. Each redundancy logic circuit corresponds to a respective column in the memory. Each column is configured to route a shift-in signal through its redundancy multiplexers during a scan mode of operation.

An integrated circuit (IC) includes first and scan latches that are enabled to load data during a first part of a clock period. A clocking circuit outputs latch clocks with one latch clock driven to an active state during a second part of the clock period dependent on a first address input. A set of storage elements have inputs coupled to the output of the first scan latch and are respectively coupled to a latch clock to load data during a time that their respective latch clock is in an active state. A selector circuit is coupled to outputs of the first set of storage elements and outputs a value from one output based on a second address input. The second scan latch then loads data from the selector's output during the first part of the input clock period.

Digital testing is performed on an integrated circuit while radiation upsets are induced at locations of the integrated circuit. For each digital test, a determination is made as to whether there is a variation in the output of the digital test from an expected output of the digital test. If there is variation, a time of the variation is indicated. In one example, a location of a defect in the digital circuit can be determined from the times of the variations. In other embodiments, a mapping of the digital circuit can be made from the times.

The present disclosure relates to a test response compaction scheme and, more particularly, to a test response compaction scheme for integrated circuits with improved diagnostic capability and test time, with related structures and processes. The method includes: arranging bits of a memory cell into channels and clock cycles, wherein each clock cycle is assigned a successive prime number and each channel has a maximum chain length of X number of bits; performing a test by applying stimulus and capturing response in memory elements; scanning out test results of the test performed on the bits for each cycle and channel; calculating a final signature of the test results using the successive prime number and a weighting afforded to each channel; and identifying any failures of the bits by comparing the final signature to an expected signature.

A programmable logic device (PLD) supports scan testing of configurable logical blocks using scannable word line (WL) shift register (WLSR) chains to enable writes to configurable memory bits while scan test data is input via a scan chain comprising scannable bit line (BL) shift registers (BLSRs). Input test data may be shifted onto BLs to write data into a configurable memory bit when a corresponding WL associated with the configurable memory bit is asserted. Logic blocks may comprise: latch-based configurable memory bits, scannable WLSRs forming a distinct WLSR chain in shift mode and driving corresponding WLs. Each WL, when asserted, enables writes to a corresponding configurable memory bit. A scannable BLSR receives serial scan test vector input in shift mode and drives a corresponding BL coupled to the configurable memory bit to write data to the configurable memory bit when the associated WL is asserted.

A register array includes a plurality of groups of latches. Each of the groups of latches includes a first latch, a second latch, and a test latch connected to the first latch and the second latch. During functional operation the first latch and the second latch process data, in response to the same read/write clock signal supplied simultaneously to the first read/write clock input and the second read/write clock input. During test operation a skewed test clock signal of an original test clock signal is supplied at different timings to the first latch, the second latch, and the test latch, and a single scan signal is input to the first latch. The single scan signal cascades from the first latch through the test latch to the second latch, and is output by the second latch, within a single cycle of the original test clock signal.

A semiconductor circuit of the disclosure includes; a sequential circuit unit including a plurality of logic circuit units that include respective flip flops and respective non-volatile storage elements, the sequential circuit unit performing, in a first term, store operation in which the storage elements in the plurality of the logic circuit units store respective voltage states in the plurality of the logic circuit units, and shift operation in which the flip flops in the plurality of the logic circuit units operate as a shift register; and a first memory that stores, in the first term, first data or second data, the first data being outputted from the shift register by the shift operation, and the second data corresponding to the first data.