The present disclosure provides a gate driving circuit, a method for detecting the gate driving circuit, an array substrate and a display apparatus. The gate driving circuit comprises a plurality of cascaded gate driving units, access units, a first signal line and a second signal line. Each access unit is connected to its corresponding gate driving unit and the gate driving unit at the next stage to its corresponding gate driving unit. The access unit corresponding to the gate driving unit at each odd stage is connected to the first signal line such that the first signal line detects an output signal from that gate driving unit via the access unit, and the access unit corresponding to the gate driving unit at each even stage is connected to the second signal line such that the second signal line detects an output signal from that gate driving unit via the access unit.

A hardware assisted scheme for testing IC memories using scan circuitry is disclosed. An IC includes a memory implemented thereon and a chain of serially-coupled scan elements to enable the inputting of test vectors. The scan elements include first and second subsets forming write and read address registers, respectively, a first control flop, and a second control flop. During a launch cycle of a test operation, a first address loaded into the write address register is provided to a write address decoder to effect a write operation. Also responsive to the launch cycle, the first control flop is configured to cause the first address to be provided to the read address register, while the second control flop causes data to be written into the memory. During a capture cycle, the first address is provided to a read address decoder and the second control flop causes a read of data therefrom.

A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

A circuit and a method for testing for faults in a circuit path. The circuit comprises a memory, a collar flop connected in parallel with the memory, and a feedback path in communication with the output of the memory and the input of the collar flop. The method comprises applying a fault test vector to logic in the circuit path to produce a fault test vector response, propagating the vector or the response through a memory in the circuit path, and capturing the response in a collar flop.

A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (MUT). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

A memory device including a first configuration bit group including a plurality of bits, the plurality of bits including: a plurality of configuration bits; at least one redundant configuration bit; a plurality of configuration bit multiplexers each configured to receive (i) a first input from a first bit in the plurality of bits and/or a second input from a second bit in the plurality of bits and (ii) a third input from a decoder, each of the first, second, and third inputs indicating a respective logical state, wherein the logical state includes a first state or a second state; and wherein, based on the logical state of the third input received from the decoder, each configuration bit multiplexer is configured to output: the logical state of the first input from the first bit, or the logical state of the second input from the second bit.

A system includes test control circuitry and a memory. The memory includes a memory array, a pre-decode circuit, and a plurality of address latches. Each address latch of the plurality of address latches is configured to operate in a scan chain of a plurality of scan chains for scan testing. A first set of the plurality of address latches each has a data input coupled to a corresponding address pin of the first memory and each has an output coupled to the pre-decode circuit. A second set of the plurality of address latches, mutually exclusive of the first set, each has a data input coupled to a data input of at least one latch in the first set of the plurality of latches and each is configured to not provide any input to the pre-decode circuit.

An array of memory cells can be configured into one or more scan chains that uses non-overlapping scan word line pulses in a direction opposite to a direction of the scan chain to shift scan bits in the direction of the scan chain from a scan chain input to a scan chain output. A memory cell may include a latch and a scan input multiplexer. The array includes a pulse generator to derive a pulse generator output from a clock pulse, and a digital delay line to generate the non-overlapping scan word line pulses from the pulse generator output. The scan chain may include a latch from an input buffer and may scan multiple columns or rows.

A method is disclosed for scanning an array of memory cells arranged in rows and columns, where the array includes a scan chain partitioned into multiple sections. Each section includes a first scan multiplexer, a section buffer cell, and multiple memory cells. The method includes determining whether a scan shift mode is entered, asserting a scan enable signal to select second inputs of each first scan multiplexer when the scan shift mode is entered, coupling the scan input with the input of the section buffer cell of the first section, and coupling the output of the memory cell in the previous section with the input of the section buffer cell in the next section. The method further includes updating the contents of the section buffer cell and the memory cells using clock signals and scan word line pulses.

A memory device can include a first portion having a memory array comprising a plurality of memory cells and a first via chain segment for performing a test operation. The memory device can include a second portion comprising processing circuitry and a second via chain segment for performing the test operation. The memory device can also include an interconnect coupling the first portion and the second portion, the interconnect comprising a third via chain segment, wherein the first via chain segment, second via chain segment, and third via chain segment can be selected independently.