A method of detecting faults in a register bank is disclosed. The register bank includes at least one chain of registers. The method comprises sequentially shifting parameters stored in each register of the chain to an output node of the chain and inverting each parameter and feeding each parameter back to an input node of that chain, and sequentially shifting the inverted parameters through the chain until all the non-inverted parameters have been output at the output node. A first checksum of the parameters output at the output node is calculated. The inverted parameters in each register of the chain are sequentially shifted to the output node of the chain. A second checksum of the inverted parameters output at the output node is calculated, and the first and second checksums are compared.

A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

A memory device, a memory system, and corresponding methods are provided. The memory device includes a non-volatile random access memory. The non-volatile memory includes a suspect bit register configured to store addresses of bits that are determined to have had errors. The non-volatile memory further includes a bad bit register configured to store addresses of bits that both (i) appeared in the suspect bit register due to a first error and (ii) are determined to have had a second error. Hence, the memory device overcomes the aforementioned intrinsic write-error-rate by identifying the bad bits so they can be fused out, thus avoiding errors during use of the non-volatile random access memory.

A semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.

A semiconductor memory device and an operating method thereof. The semiconductor memory device includes a memory cell array, a peripheral circuit and a control logic. The memory cell array includes a plurality of memory cells. The peripheral circuit performs a program operation for the plurality of memory cells in the memory cell array. The control logic controls the peripheral circuit and the memory cell array such that, during the program operation for the plurality of memory cells, pre-bias voltages are applied to a plurality of word lines coupled to the plurality of memory cells to precharge channel regions of the plurality of memory cells. Furthermore, different pre-bias voltages are applied to the plurality of word lines depending on the relative positions of the word lines.

A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.

A sequence of contiguous pages in an erase block in a non-volatile memory device is programmed and erased. Next, all of the pages in the erase block are programmed with data. Then, the data is read back and verified to determine whether there is an error in the data. When there is an error in the data, then the last page in the sequence is identified as being unstable. If there is no error in the data, then the last page in that sequence is identified as being stable. Thus, the recorded information identifies a point of instability in the erase block. Instabilities can be stabilized by performing additional writes to fill the partially filled word line.

A logic circuit is provided including at least two input cells and a sense circuit. The input cells are connected to a common result line. Further, the input cells are operable for influencing an electrical quantity at the result line. The sense circuit is connected to the result line, and is adapted to output a discrete value out of more than two possible values based on the electrical quantity.

A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory configurations based on a plurality of translation tables used by a stimuli generator to solve a plurality of test templates, providing a test template from the plurality of test templates, selecting a memory configuration from the plurality of memory configurations based on the test template, a memory variable, and a set of testing parameters, identifying a translation table from the plurality of translation tables based on the test template, allocating a memory space for the translation table, and executing the test template on the stimuli generator based on the translation table, the memory space, and the set of testing parameters.

A method for generating address translation stimuli for post-silicon functional validation is provided. The method includes determining a plurality of memory configurations based on a plurality of translation tables used by a stimuli generator to solve a plurality of test templates, providing a test template from the plurality of test templates, selecting a memory configuration from the plurality of memory configurations based on the test template, a memory variable, and a set of testing parameters, identifying a translation table from the plurality of translation tables based on the test template, allocating a memory space for the translation table, and executing the test template on the stimuli generator based on the translation table, the memory space, and the set of testing parameters.