A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

An integrated circuit (IC) having a scan compression architecture includes decompression logic coupled between test access input and a block of IC elements (e.g. flip-flops) coupled together to define a plurality of scan paths. The block of IC elements includes an initial data selector at an initial position of each of the scan paths, and an additional data selector downstream within at least one of the scan paths and configured to reconfigure an order of the IC elements within the at least one scan path. Compression logic is coupled between the block of IC elements and a test access output.

Provided is a semiconductor storage apparatus having a storage apparatus driving circuit which can efficiently perform screening tests for the semiconductor memory device. A semiconductor memory device includes a wright-voltage supply circuit, a wright-voltage switching circuit, a bit line discharge control circuit, a bit line discharge circuit, and a memory array. The wright-voltage supply circuit is connected to the memory array through the wright-voltage switching circuit. The bit line discharge control circuit is connected to the memory array through the bit line discharge circuit.

Provided is a semiconductor storage apparatus having a storage apparatus driving circuit which can efficiently perform screening tests for the semiconductor memory device. A semiconductor memory device includes a wright-voltage supply circuit, a wright-voltage switching circuit, a bit line discharge control circuit, a bit line discharge circuit, and a memory array. The wright-voltage supply circuit is connected to the memory array through the wright-voltage switching circuit. The bit line discharge control circuit is connected to the memory array through the bit line discharge circuit.

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.