Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

Various implementations described herein refer to a device having an encoder coupled to memory. The ECC encoder receives input data from memory built-in self-test circuitry, generates encoded data by encoding the input data and by adding check bits to the input data, and writes the encoded data to memory. The device may have an ECC decoder coupled to memory. The ECC decoder reads the encoded data from memory, generates corrected data by decoding the encoded data and by extracting the check bits from the encoded data, and provides the corrected data and double-bit error flag as output. The ECC decoder has error correction logic that performs error correction on the decoded data based on the check bits, wherein if the error correction logic detects a multi-bit error in the decoded data, the error correction logic corrects the multi-bit error in the decoded data to provide the corrected data.

A computer-implemented method for sorting non-volatile random access memories (NVRAMS) includes testing a failure metric for each of a plurality of NVRAMS over a plurality of testing sessions to capture failure metric data that corresponds to the plurality of NVRAMS. The method also includes determining a trend in the failure metric as a function of testing cycles for each of the plurality of NVRAMS from the failure metric data, and separating the plurality of NVRAMS into groups based on the trend in the failure metric as a function of testing cycles. A corresponding computer program product and computer system are also disclosed herein.

System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.

System, method and computer program product for prioritizing trial-and-error attempted corrections of bit/s, in a memory, in which logical bit levels are determined by thresholding voltage values using threshold/s, the method comprising ranking bits such that a first bit is ranked before a second bit, which is less likely than said first bit to be erroneous and sequentially attempting to correct the bits in order of the ranking, including attempting to correct the first bit before attempting to correct the second bit.

An in-memory computing device includes a memory array, a multiple row decoder and a sensing circuit. The memory includes non-destructive memory cells, each of which includes an 8T-SRAM to store a bit of data. Each cell is connected to a read word line and a write word line, both connecting a row of said memory cells, a write bit line and a complementary write bit line, and a read bit line connecting a single column of said memory cells. The multiple row decoder activates at least two read word lines at a same time. The sensing circuit detects a signal on each of the selected read bit lines of multiple selected columns for reading. Each signal is a Boolean function of the stored data in the memory cells in its column activated by the activated read word lines.

An in-memory computing device includes a memory array, a multiple row decoder and a sensing circuit. The memory includes non-destructive memory cells, each of which includes an 8T-SRAM to store a bit of data. Each cell is connected to a read word line and a write word line, both connecting a row of said memory cells, a write bit line and a complementary write bit line, and a read bit line connecting a single column of said memory cells. The multiple row decoder activates at least two read word lines at a same time. The sensing circuit detects a signal on each of the selected read bit lines of multiple selected columns for reading. Each signal is a Boolean function of the stored data in the memory cells in its column activated by the activated read word lines.

Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

Disclosed is an in-memory computing device including a memory array with non-volatile memory cells arranged in rows and columns; a multiple row decoder to activate at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and circuitry to write data associated with the parametric change into the memory array. Additionally disclosed is a method of computing inside a memory array including non-volatile memory cells arranged in rows and columns, the method includes activating at least two cells in a column of the memory array at the same time to generate a parametric change in a bit line connected to at least one cell in the column; and writing data associated with the parametric change into the memory array.

A memory system may include: an error correction code (ECC) generation circuit suitable for generating an M-bit error correction code using N-bit data, where N and M are positive integers; a memory core suitable for storing the N-bit data and the M-bit error correction code; and an ECC circuit suitable for correcting an error of the N-bit data read from the memory core, using the M-bit error correction code read from the memory core, wherein the ECC generation circuit generates the M-bit error correction code using an M(N+M) check matrix, wherein one column vector among M column vectors corresponding to the M-bit error correction code in the M(N+M) check matrix has an odd weight, and the other M column vectors have even weights.