A storage device for generating an identity code, includes a first storage circuit, a second storage circuit and a reading circuit. The first storage circuit stores several first data having several bits. The second storage circuit stores several second data having several bits. The reading circuit reads the second data from the second storage circuit to form a first sequence, and simultaneously reads the first data from the first storage circuit to form a second sequence. The reading circuit includes a processing circuit which simultaneously receives the first sequence and the second sequence, selects a first portion of the second sequence to form a target sequence according to the first sequence, and outputs the target sequence to serve as an identity code. Logical values of the bits of the first data and the second data are randomly distributed or pre-defined by a user.

Embodiments relate methods and computer program products for performance testing of a solid state memory devices. The method includes operating a first solid state memory device for a period of time and capturing state information of the first solid state memory device after the period of time. The method also includes storing the state information in a control file and loading the control file onto a second solid state memory device. Once the control file has been loaded into the second solid state memory device the state information can be adapted to fix any issues due to physical variation. Performance testing can then be preformed on the second solid state memory device without preconditioning the second solid state memory device.

A nonvolatile memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a row decoder configured to select one of the plurality of wordlines in response to an address, and a wordline leakage current detector configured to determine whether the selected wordline is defective using trim information related to a level of a reference voltage or a gradient of a detect voltage during a test operation, wherein the trim information is stored internally in an electrical die sorting (EDS) process.

An integrated circuit (IC) is provided for in-situ anomaly detection. Sensors in the IC generates sensor datasets including information indicating conditions in the IC. A processing unit in the IC uses a sensor dataset and a model to detect and classify the anomaly. The processing unit may filter the sensor dataset, extract features from the filtered sensor dataset, and input the features into the model. The model outputs one or more classifications of the anomaly. A feature may be a distance vector that represents a difference between a data value in the filtered sensor dataset from a reference data value. The model may be a network of bit-cells in the IC. The model may be continuously trained in-situ, i.e., on the IC. The processing unit may provide the classifications to another processing unit in the IC. The other processing unit may mitigate the anomaly based on the classifications.

A storage device includes a first nonvolatile memory that includes a plurality of memory blocks including a first memory block and a second memory block, generates a reference counting value by counting the number of stuck bits associated with the first and second memory blocks at a first power-on, and generates one or more comparison counting values by repeatedly counting the number of the stuck bits at one or more time points after the first power-on, and a memory controller that receives the reference counting value and the one or more comparison counting values from the first nonvolatile memory, generates one or more comparison result data by comparing the reference counting value with each of the one or more comparison counting values, and repeatedly performs a chip verification operation on the first nonvolatile memory based on each of the one or more comparison result data.

A nonvolatile memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a row decoder configured to select one of the plurality of wordlines in response to an address, and a wordline leakage current detector configured to determine whether the selected wordline is defective using trim information related to a level of a reference voltage or a gradient of a detect voltage during a test operation, wherein the trim information is stored internally in an electrical die sorting (EDS) process.

Built-in self-test circuitry is configured to calculate a sensed temperature using an MRAM and a stored set of margin read reference and temperature correlations for a target bit error rate. A current margin read reference is selected, and a sweep through a sequence of addresses of the MRAM is performed using the current margin read reference. At each address of the sequence, a normal read is performed to obtain normal read data and a margin read is performed to obtain margin read data. A bit error count is obtained for the sweep based on comparisons between the normal and margin read data obtained at each address, and the current margin read reference is selectively modified based on whether or not the bit error count achieves the target bit error rate. The selectively modified current margin read reference and the stored set of correlations are used to calculate the sensed temperature.

A test circuit including a test core configured to set a charging current quantity as a first value and perform charging and discharging on a test node of a test target circuit during a first measurement interval and configured to change the charging current quantity from the first value to a second value and perform charging and discharging on the test node during a second measurement interval, and an operation circuit configured to generate a first counting value by counting a clock signal during the first measurement interval, generate a second counting value by counting the clock signal during the second measurement interval, generate the results of an operation of the first counting value and the second counting value as operation results, and output at least one of the first counting value, the second counting value, and the operation results as test result information.