An aspect relates to an integrated circuit (IC), including: a data path; a logic gate including a first input coupled to the data path, and a second input configured to receive a second input configured to receive a test data register (TDR) signal; and a first flip-flop including a data input coupled to an output of the logic gate. Another aspect relates to integrated circuit (IC), including: a first logic gate including a first input configured to receive a test data register (TDR) signal; a first flip-flop including a data input (D) coupled to an output of the first logic gate, and a data output (Q) coupled to a second input of the first logic gate; a first data path; and a second logic gate including a first input coupled to the data output of the first flip-flop and a second input coupled to the first data path.

A JTAG interface in an IC includes a test mode select (TMS) pin receiving a TMS signal, a testing test access port (TAP) having a TMS signal input, a debugging test access port (TAP) having a TMS signal and glue logic coupled to receive a first output from the testing TAP and a second output from the debugging TAP. A flip-flop receives input from the testing TAP and the debugging TAP through the glue logic. A first AND gate has output coupled to the TMS signal input of the debugging TAP, and receives input from an output of the flip-flop and the TMS signal. An inverter has an input coupled to receive input from the flip-flop. A second AND gate has output coupled to the TMS signal input of the testing TAP, and receives input from the TMS signal and output of the inverter.

A circuit is for coupling test access port (TAP) signals to a Joint Test Action Group (JTAG) interface in an integrated circuit package. An nTRST pin receives a test reset signal, a TMS pin receives a test mode select signal, a testing test access port (TAP) has a test reset signal input and a test mode select signal input, and a debuging test access port (TAP) has a test reset signal input coupled to the nTRST pin and a test mode select signal input coupled to the TMS pin. An inverter has an input coupled to the nTRST pin and an output coupled to the test reset signal input of the testing TAP, and an AND gate has a first input coupled to the output of the inverter, a second input coupled to the TMS pin, and an output coupled to the test mode select input of the testing TAP.

The disclosure describes a novel method and apparatus for improving silicon interposers to include test circuitry for testing stacked die mounted on the interposer. The improvement allows for the stacked die to be selectively tested by an external tester or by the test circuitry included in the interposer.

According to one embodiment, there is provided a common test board including a socket board, an IP evaluation board, and a common board. To the socket board, a semiconductor device is to be connected. On the IP evaluation board, the socket board is able to be attached. On the common board, the IP evaluation board is able to be attached.

Control events may be signaled to a target system having a plurality of components coupled to a scan path by using the clock and data signals of the scan path. While the clock signal is held a high logic level, two or more edge transitions are detected on the data signal. The number of edge transitions on the data signal is counted while the clock signal is held at the high logic state. A control event is determined based on the counted number of edge transitions on the data signal after the clock signal transitions to the low logic state.

The disclosure describes a novel method and apparatus for testing different types of TSVs in a single die or different types of TSV connections in a stack of die. The testing is facilitated by test circuitry associated with each type of TSV. The test circuitry includes a scan cell adapted for testing TSVs.

According to one embodiment, there is provided a common test board including a socket board, an IP evaluation board, and a common board. To the socket board, a semiconductor device is to be connected. On the IP evaluation board, the socket board is able to be attached. On the common board, the IP evaluation board is able to be attached.

A Scan test in a single-wire bus circuit is described in the present disclosure. The single-wire bus circuit has only one external pin for connecting to a single-wire bus. Given that multiple physical pins are required to carry out the Scan test, the single-wire bus circuit must provide additional pins required by the Scan test. In embodiments disclosed herein, the single-wire bus circuit includes a communication circuit under test, and a driver circuit coupled to the communication circuit via multiple internal pins. The driver circuit uses a subset of the internal pins as input pins and another subset of the internal pins as output pins to carry out the Scan test in the communication circuit. As a result, it is possible to perform the Scan test without adding additional external pins to the single-wire bus circuit, thus helping to reduce complexity and footprint of the single-wire bus circuit.

Scan forest can effectively compress test data volume, however, CPU time and memory consumption must be well-controlled to handle industrial designs. The present disclosure provides a method to establish a scan forest, which reduces memory consumption and CPU time significantly. A new low-power test application scheme is proposed, which does not need to increase the test application cost but can be of help to compress test data volume. Another new test application algorithm is proposed to reduce capture cycle power and shift cycle power by just doubling the test application time, which does not sacrifice the test data compression performance.