Testability of memory on integrated circuits is improved by connecting storage elements like latches in memory to scan chains and configuring memory for scan dump. The use of latches and similar compact storage elements to form scannable memory can extend the testability of high-density memory circuits on complex integrated circuits operable at high clock speeds. A scannable memory architecture includes an input buffer with active low buffer latches, and an array of active high storage latches, operated in coordination to enable incorporation of the memory into scan chains for ATPG/TT and scan dump testing modes.

An implementation of a system disclosed herein includes a decompressor logic with the capability to vary a level of decompression of a scanning input signal based on value of compression program bits and a compressor logic to generate a scanning output signal, the compressor logic including a plurality of XOR logics, wherein the output of the plurality of XOR logics is selected based on the compression program bits.

According to one embodiment, a semiconductor integrated circuit includes: a first core that includes a first logic circuit that has a plurality of first scan chains, and a first generator that generates a first test pattern; a second core that includes a second logic circuit that has a plurality of second scan chains, and a second generator that generates a second test pattern; a controller that controls a test operation of the first and second cores. The controller is configured to: obtain a seed for a test pattern from the first generator; supply the obtained seed to the second generator; perform a test on the first and second cores for a same number of cycles; obtain first and second test results respectively from the first and second cores; and compare the first and second test results.

A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.

A method of identifying cell-internal defects: obtaining a circuit design of an integrated circuit, the circuit design including netlists of one or more cells coupled to one another; identifying the netlist corresponding to one of the one or more cells; injecting a defect to one of a plurality of circuit elements and one or more interconnects of the cell; retrieving a first current waveform at a location of the cell where the defect is injected by applying excitations to inputs of the cell; retrieving, without the defect injected, a second current waveform at the location of the cell by applying the same excitations to the inputs of the cell; and selectively annotating, based on the first current waveform and the second current waveform, an input/output table of the cell with the defect.

The disclosure describes novel methods and apparatuses for accessing test compression architectures (TCA) in a device using either a parallel or serial access technique. The serial access technique may be controlled by a device tester or by a JTAG controller. Further the disclosure provides an approach to access the TCA of a device when the device exists in a daisy-chain arrangement with other devices, such as in a customer's system. Additional embodiments are also provided and described in the disclosure.

This application discloses a computing system implementing an automatic test pattern generation tool to perform scan chain diagnosis-driven compaction setting. The computing system can perform fault simulation on scan chains in a circuit design describing an integrated circuit, which loads test patterns to the simulated scan chains and unloads test responses from the simulated scan chains. The computing system can determine locations of sensitive bits and locations of unknown bits in each of the scan chains based on the test responses from the simulated scan chains, and generate a configuration for a compactor in the integrated circuit based, at least in part, on the locations of the sensitive bits and the locations of the unknown bits in each of the scan chains, wherein the compactor is configured to compact test responses from the scan chains in the integrated circuit based on the configuration.

Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

A software-defined linear feedback shift register (SLFSR) implements a low-power test compression for launch-on-capture (LOC). Each bit of an extra register controls a stage of the SLFSR. A control vector is shifted into the extra register to indicate whether a primitive polynomial contains the stage of the non-zero bit. Therefore, SLFSR can configure any primitive polynomials with different degrees by loading different control vectors without any hardware overhead. A low-power test compression method and design for testability (DFT) architecture provide LOC transition fault testing by using seed encoding scheme, low-power test application procedure and a software-defined linear-feedback shift-register (SLFSR) architecture. The seed encoding scheme generates seeds for all test pairs by selecting a primitive polynomial that encodes all test pairs of a compact test set.

A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.