A test pattern is shifted into scan chains in a circuit in a first direction. The scan cells on each of the scan chains are further coupled to corresponding scan cells on two other scan chains in the scan chains such that data bits stored in the scan cells can be shifted circularly in a second direction orthogonal to the first direction based on a control signal. The loaded test pattern is then shifted in the second direction for a number of clock cycles equal to the number of the scan chains. The test pattern is then shifted in the first direction out of the scan chains to generate a chain test result. Faulty scan cell candidates on faulty scan chains may be determined based on part of the chain test result for one of good scan chains.

A semiconductor integrated circuit includes: scan chains each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an ICG chain composed by coupling, to one another, ICG circuits each of which individually supplies any of the scan chains with a circuit clock signal for operating the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at pieces of timing which are different between the scan chains.

A circuit includes a test data input (TDI) pin receiving a test data input signal, a test data out (TDO) pin outputting a test data output signal, and debugging test access port (TAP) having a test data input coupled to the TDI pin and a bypass register having an input coupled to the test data input of the debugging TAP. A multiplexer has inputs coupled to the TDI pin and the debugging TAP. A testing TAP has a test data input coupled to the output of the multiplexer, and a data register having an input coupled to the test data input of the testing TAP. The multiplexer switches so the test data input signal is selectively coupled to the input of the data register of the testing TAP so the output of the debugging TAP is selectively coupled to the input of the data register of the testing TAP.

According to one embodiment, a semiconductor integrated circuit includes: a logic circuit including a first scan chain configured to operate based on a first clock signal and a second scan chain configured to operate based on a second clock signal in a built-in self-test; a pattern generator configured to generate a test pattern and transmit the test pattern to the first and second scan chains; a compression circuit configured to compress first data received from the first and second scan chains; a clock select circuit configured to select one of the first and second clock signals and transmit the one of the first and second clock signals to the corresponding one of the first and second scan chains in the test; and a test control circuit configured to control the test and detect a fault in the logic circuit based on a result of the test.

A method for testing a many-core processor comprises grouping a plurality of cores in the processor into a plurality of super cores, wherein each super core comprises one or more scan chains that propagate through a respective super core. Further, the method comprises grouping the plurality of super cores into a plurality of clusters. The method also comprises comparing one or more scan chain outputs of respective super cores in each cluster using a network of XOR and OR gates to generate a single bit fault signature for each scan chain in a respective cluster and compacting the single bit fault signatures for each scan chain using a hybrid of spatial and temporal compactors to generate a single bit fault signature for each cluster. The method also comprises method of using a cost function to obtain hierarchical parameters to achieve optimized ATPG effort, area overhead and test time.

The present invention provides a method, device, and system for testing devices under testing (DUTs). The method comprises: sending a scan activated signal and a synchronous clock signal via the second signal line, and sending a first preset signal via the serial signal line, wherein each bit of the first preset signal is transmitted to a corresponding scan chain unit in a sequence of serial connection of the plurality of scan chain units with according to the synchronous clock signal, the corresponding scan chain unit is one of the plurality of scan chain units connected serially and coupled to the plurality of DUTs via a third signal line; sending a scan deactivated signal via the second signal line, to deactivate the scan chain units from identifying and receiving the first preset signal; and sending a second preset signal via the second signal line, and sending a test signal via the first signal line.

A device test architecture and interface is provided to enable efficient testing embedded cores within devices. The test architecture interfaces to standard IEEE 1500 core test wrappers and provides high test data bandwidth to the wrappers from an external tester. The test architecture includes compare circuits that allow for comparison of test response data to be performed within the device. The test architecture further includes a memory for storing the results of the test response comparisons. The test architecture includes a programmable test controller to allow for various test control operations by simply inputting an instruction to the programmable test controller from the external tester. The test architecture includes a selector circuit for selecting a core for testing. Additional features and embodiments of the device test architectures are also disclosed.

A chip testing method including the following operations is disclosed: outputting a plurality of testing sequences to a plurality of scan chains by an encoding circuit; generating a plurality of scan output data according to the plurality of testing sequences by the plurality of scan chains; and determining whether the plurality of scan chains exist an error according to the plurality of scan output data by a decoding circuit.

A system, apparatus, and method of testing a plurality of test circuits is disclosed that includes inputting experiment data to the plurality of test circuits; applying a control signal to each of the plurality of test circuits to control application of the experiment data to the plurality of test circuits; and shifting the control signal in response to applying the control signal to each of the plurality of test circuits so that a different bit of the control signal is applied to each of the plurality of test circuits. The method in an aspect further comprises reading out a data out signal from each of the plurality of test circuits; and shifting the data out signal in response to reading out the data out signal from each of the plurality of test circuits.

Certain aspects of the present disclosure provide a circuit for testing processor cores. For example, certain aspects provide a circuit having a deserializer having at least one input coupled to at least one input node of the circuit and having a first plurality of outputs, a plurality of processor cores having inputs coupled to the first plurality of outputs of the deserializer, and a serializer having inputs coupled to a second plurality of outputs of the plurality of processor cores.