A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

Sensor data relating to operating conditions for an integrated circuit are read out through scan chains. Scan tests are run on an integrated circuit containing logic circuits that implement logic functions. The logic circuits are interconnected to form scan chains which are used in running the scan tests. The scan test data resulting from the scan tests is read out from the logic circuits through these scan chains. During the scan tests, sensor blocks capture measurements of the operating conditions for the logic circuits. The operating conditions may include process, voltage and/or temperature conditions, for example. The sensor blocks are also interconnected to form one or more scan chains, and sensor data produced from the captured measurements is read out through these scan chains concurrently with the read out of the scan test data.

A fast Mux-D scan flip-flop is provided, which bypasses a scan multiplexer to a master keeper side path, removing delay overhead of a traditional Mux-D scan topology. The design is compatible with simple scan methodology of Mux-D scan, while preserving smaller area and small number of inputs/outputs. Since scan Mux is not in the forward critical path, circuit topology has similar high performance as level-sensitive scan flip-flop and can be easily converted into bare pass-gate version. The new fast Mux-D scan flip-flop combines the advantages of the conventional LSSD and Mux-D scan flip-flop, without the disadvantages of each.

A semiconductor device has a cell region including active regions that extend in a first direction and in which are formed components of transistors. The transistors of the cell region are arranged to function as a scan insertion D flip flop (SDFQ). The SDFQ includes a multiplexer serially connected at an internal node to a D flip-flop (FF). The transistors of the multiplexer include data transistors for selecting a data input signal, the data transistors having a first channel configuration with a first channel size, and scan transistors of the multiplexer for selecting a scan input signal, the scan transistors having a second channel configuration with a second channel size. The second channel size is smaller than the first channel size.

A system, method and apparatus for mixer phase response measurement comprises a vector network analyzer connectable to a device under test, an additional device connected to the analyzer the additional device configured to have an equal phase response to that of the device under test, a local oscillator connected to the device under test and the additional device, a series of switches connecting the device under test and the additional device to a vector voltmeter, and a reference generator connected to the vector voltmeter.

A system, method and apparatus for mixer phase response measurement comprises a vector network analyzer connectable to a device under test, an additional device connected to the analyzer the additional device configured to have an equal phase response to that of the device under test, a local oscillator connected to the device under test and the additional device, a series of switches connecting the device under test and the additional device to a vector voltmeter, and a reference generator connected to the vector voltmeter.

One exemplary embodiment describes an integrated circuit, comprising a multiplicity of scan flip-flops, a multiplicity of ring oscillator circuits, wherein each ring oscillator circuit comprises a chain of logic gates comprising a plurality of logic gates connected in succession, an input multiplexer for the chain, and a feedback line from an output connection of the last logic gate of the chain to a data input connection of the input multiplexer. Each ring oscillator circuit is assigned a scan flip-flop group that contains at least one of the multiplicity of scan flip-flops. The input multiplexer of the ring oscillator circuit is controlled depending on a control bit stored by the at least one scan flip-flop of the scan flip-flop group assigned to the ring oscillator circuit such that the input multiplexer outputs an output bit fed back via the feedback line to the first logic gate of the chain or that the input multiplexer outputs a input bit that is to be processed by the chain to the first logic gate of the chain. The ring oscillator circuits are assigned different scan flip-flop groups.

A circuit includes a dynamic core data register (DCDR) cell that includes a data register, a shift register and an output circuit to route the output state of the data register or the shift register to an output of the DCDR in response to an output control input. A clock gate having a gate control input controls clocking of the shift register in response to a first scan enable signal. An output control gate controls the output control input of the output circuit and controls which outputs from the data register or the shift register are transferred to the output of the output circuit in response to a second scan enable signal. The first scan enable signal and the second scan enable signal to enable a state transition of the shift register at the output of the DCDR.

A semiconductor device includes a processing block which comprises one or more intellectual property (IP) blocks; a scan chain which is electrically connected to the IP blocks, wherein the scan chain block has a scan in (SI) terminal and a scan out (SO) terminal; a pattern generating circuit which generates a data pattern having a plurality of bits and inputs the data pattern to the scan in (SI) terminal of the scan chain; and an analyzing circuit which determines the degree of degradation of each of the IP blocks based on a result pattern output from the scan out (SO) terminal of the scan chain.

Implementations described herein relate to a core and interface scan testing. In some implementations, an integrated circuit may include input scan flip-flops (ISFFs) arranged in multiple ISFF stages that include a first ISFF stage and a second ISFF stage. Inputs to the first ISFF stage are connected to inputs of the integrated circuit. Inputs to the second ISFF stage are connected to outputs of a logic component that is connected to outputs of the first ISFF stage. The integrated circuit may include output scan flip-flops (OSFFS) arranged in multiple OSFF stages that include a first OSFF stage and a second OSFF stage. Outputs from the first OSFF stage are connected to outputs of the integrated circuit. Outputs from the second OSFF stage are connected to inputs of a logic component that is connected to inputs of the first OSFF stage. The integrated circuit may include core scan flip flops.