A semiconductor device includes first active regions extending in a first direction and having a first number of fins; second active regions extending in the first direction and having a second number of fins, the second number of fins being less than the first number of fins; data transistors formed at least in part in the first active regions; and scan transistors formed at least in part in the second active regions. The data transistors and the scan transistors are included in a scan insertion D flip-flop (SDFQ) that includes a multiplexer serially connected at an internal node to a D flip-flop (FF), the multiplexer including the data transistors for selecting a data input signal, and including the scan transistors for selecting a scan input signal.

A method for implementing a programmable critical delay path measurement in-line with the critical path logic cells. Additionally, the delay measurement creates a code to be used with a programmable DLL which indicates the delay of the measured critical path. This code can also be used by an off line First Fail Circuit which can mimic the delay of the critical path and give an indication of the critical path delay. The target of this invention is to create a method to optimize the required operating voltage of an integrated circuit per specific speed requirement, overcoming different process variations, temperatures changes and in die variations.

An integrated circuit is provided. For example, an integrated circuit comprises a functional data path and a scan-data path. At least a portion of the scan-data path is separate from the functional data path. The portion of the scan-data path which is separate from the functional data path comprises a combined gating/delay element for preventing a scan-data signal from reaching any elements downstream of the combined gating/delay element during a scan mode and for providing some or all of a desired signal delay in the portion of the scan-data path which is separate from the functional data path.

A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n1 and said layer n.

A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n1 and said layer n.

A design-for-test (DFT) architecture for testing a three dimensional (3D) integrated circuit, may comprise a two dimensional (2D) silicon layer n1 and a 2D silicon layer n connected together with a through silicon via (TSV) having a first side and a second side; scannable latch circuits on said first side and said second side of said TSV, wherein said scannable latch circuits: control flow of data between said layer n1 and said layer n and allow said TSV to be verified; allow launch and capture clocks to be applied with variable delay in order to perform an alternating current delay fault test between said layer n1 and said layer n; and have a quiescent state supply current (IDDq) test function built in which allows selection of an input load for a unidirectional signal connection between said layer n1 and said layer n.

A serial interface circuit includes an input/output (I/O) port to receive data and a control circuit configured to load a delay metric for the serial interface circuit, transmit first control information of the delay metric to a monitor circuit to cause the monitor circuit to generate a plurality of delay time measurement values, sort the plurality of delay time measurement values to generate sorted values, generate a look-up table (LUT) by mapping the sorted values to indices and transmit the LUT to the monitor circuit.

An electronic system, comprising a critical logic circuit, various scan chains, and a control circuit, is provided. The critical logic circuit includes a critical path. One or more scan chains of the electronic system are coupled to the critical logic circuit and are associated with sensitization of the critical path. The control circuit may receive one or more configuration datasets, where each configuration dataset includes a scan chain identifier and a test pattern. For each received configuration dataset, the control circuit may identify a scan chain, of the one or more scan chains, that is associated with the scan chain identifier, and load the identified scan chain with the test pattern. Some scan flip-flops of the loaded one or more scan chains are utilized to sensitize the critical path.