A scan reset control circuit includes a single scan reset input configured to receive a reset signal, a plurality of scan reset outputs configured to be coupled to a plurality of circuit blocks in a one-to-one ratio, a plurality of writable non-scan test data registers including register outputs configured to assert or deassert the reset signal, and a plurality of reset enable circuits coupled to the plurality of scan reset outputs in a one-to-one ratio. Each of the scan reset outputs is configured to simultaneously reset a set of scan flip-flops of the corresponding circuit block. Each of the plurality of reset enable circuits includes an input coupled to the single scan reset input, a selector input coupled to the register outputs, and an output coupled to the corresponding scan reset output.