A scan flip-flop configured to generate physically unclonable function (PUF) data according to the present disclosure includes a multiplexer configured to provide an internal signal through an input switch, a first latch circuit configured to latch the internal signal, wherein the first latch circuit comprises a first inverter, a second inverter, a first switch connected in parallel with the first inverter, and a second switch connected in series with the second inverter. Additionally, a second latch circuit configured to latch an output of the first latch circuit and output a latched value, wherein the second latch circuit comprises a third inverter, a fourth inverter, an output inverter connected in series with the third inverter, and a fourth switch connected in series with the fourth inverter. A third switch is configured to switch between the first latch circuit and the second latch circuit.

A semiconductor device includes a scan data output and a scan chain having length n. Scan data bits appear sequentially at the scan data output responsive to a scan clock when the device is in a scan mode. Initial masking circuitry is operable to obscure, responsive to the device transitioning from a non-scan mode to the scan mode, a first n bits of the scan data appearing at the scan data output and not to obscure n+1st and subsequent bits of the scan data appearing at the scan data output. Infinite masking circuitry is operable to obscure, responsive to an infinite masking trigger, all scan data bits appearing at the scan data output until a reset of the device occurs. Monitoring and security enforcement circuitry is operable to detect a configuration change and to generate the infinite masking trigger if the detected change corresponds to a potential security risk.

The present application discloses a debug system. The debug system includes a DTM, a first DM, a second DM, and a module selector. The first DM is coupled to a first processing core, and the second DM is coupled to a second processing core. The module selector is coupled to the DTM, the first DM, and the second DM. When a selection data register of the DTM is written with a first value, the DTM controls the module selector to select a first path coupled between the DTM and the first DM so as to access the first processing core through the first path. When the selection data register is written with a second value, the DTM controls the module selector to select a second path coupled between the DTM and the second DM so as to access the second processing core through the second path.

In one embodiment, a method includes: receiving, in a replica circuit associated with a first intellectual property (IP) circuit of a system on chip (SoC), a security policy; receiving, in the replica circuit, a test data register access message to identify an access to a first test data register of the first IP circuit; and preventing the access to the first test data register based at least in part on the security policy. Other embodiments are described and claimed.