An automotive control system includes a safety processor and a system-on-a-chip. The SoC includes a primary processor, a safety monitor, first and second GPIO banks, and a debug interface. The safety monitor is configured to detect a fault condition of the primary processor and to provide an indication of the fault condition to the safety processor. The first GPIO bank is coupled to the primary processor to provide input/output operations to a non-critical function of an automobile, while the second GPIO bank is coupled for a critical function of the automobile. The debug interface is coupled to the second GPIO bank to form a scan chain with input and output registers of the second GPIO bank, and is coupled to the safety processor to receive control information for the scan chain to provide input/output operations to the critical function of the automobile when the safety monitor provides the indication.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

A sensor system can include a sensor having a charge storage device controllably connected to a voltage source under control of a signal under test; and a readout circuit coupled to the charge storage device to determine whether the pulse width of the signal under test has changed greater than a threshold amount according to a voltage at the charge storage device. In some cases, the determination of whether the pulse width of the signal under test has changed can include determining whether the voltage satisfies a condition with respect to a comparison voltage. In some cases, the determination of whether the pulse width of the signal under test has changed can be based on a propagation delay through a delay chain, where the propagation delay is dependent on the voltage.

A network of storage units has a data path, which is at least a portion of the network. The network also has a dynamic time-varying or cycle-varying code generation unit and a code comparator unit that together make up an unlock signal generation unit; and a gateway storage unit. If the gateway storage unit does not store an unlock signal or the unlock signal generation unit does not generate and transmit an unlock signal, the gateway storage unit does not insert a data path segment in the data path. If the unlock signal generation unit is operated such that it generates an unlock signal, and it transmits that unlock signal to a gateway storage unit, and the gateway storage unit stores the unlock signal value, then the gateway storage unit inserts a data path segment into the data path.

Devices, methods, and computer program products for detecting Points Of Failures in an integrated circuit (IC) are provided. The integrated circuit device is described by a structural description (2) comprising a plurality of elements, the elements representing cells and wires interconnecting the cells, the structural description further comprising portions representing a set of sensitive functional blocks (16), each sensitive functional block comprising one or more inputs, at least one sensitive output, and a set of elements interconnected such that the value of the sensitive output is a Boolean function of the input values of the sensitive functional block. The detection device (100) comprises: a selection unit (101) configured to iteratively select a n-tuple of elements in at least the portions of the netlist corresponding to said sensitive functional blocks, a testing unit (104) configured to test each selected n-tuple of elements, the testing unit being configured to: modify said selected n-tuple of elements from an initial state to a testing state; determine if the derivative of the Boolean function associated with each sensitive functional block is equal to zero. The detection device (100) is configured to detect that said n-tuple represents a Point Of Failure of order n in the integrated circuit (IC) device if the derivative of the Boolean function associated with said sensitive functional block is equal to zero.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Systems, methods, and apparatuses are described for verifying the authenticity of an integrated circuit device. An integrated test apparatus may use quiescent current and/or conducted electromagnetic interference readings to determine if a device under test matches the characteristics of an authenticated device. Deviations from the characteristics of the authenticated device may be indicative of a counterfeit device.

Various examples of a circuit and a technique for testing the circuit are disclosed herein. In an example, the circuit includes a data input coupled to a scan multiplexer and a path select multiplexer. The circuit further includes a scan-in input coupled to the scan multiplexer and to receive a value of a scan pattern. The circuit further includes a scan latch to store the value that has an input coupled to the scan multiplexer and an output coupled to the path select multiplexer. The scan multiplexer selects a first signal from the data input and the scan-in input and provides the first signal to the input of the scan latch. The path select multiplexer selects a second signal from the data input and the output of the scan latch and provides the second signal to a data output of the circuit.

A Joint Test Action Group (JTAG) communication lockout processor is disclosed. The processor is configured to generate a unlock sequence based on an operational mode change of an operably connected programmable device, and save the unlock sequence to one or more memory registers. The processor can also receive an execution of the unlock sequence via a dual function JTAG communication bus, determine, via an unlock logic, whether the execution of the unlock sequence is valid, and responsive to determining that the execution of the unlock sequence is valid, allow or disallow the JTAG communication with an embedded processor.

A device includes a scan chain including a plurality of storage elements and an output buffer; a shadow shift register having a shadow shift input coupled to a scan output of one of the storage elements of the scan chain; a signature register; and a comparator having a first input, a second input, and an output. The comparator first input is to receive a value of the shadow shift register, and the comparator second input is to receive a value of the signature register. The output buffer has a control input coupled to the comparator output, and the output buffer provides a high-impedance output responsive to the value of the shadow shift register being unequal to the value of the signature register.