The JTAG debug apparatus includes: a TAP controller, configured to communicate with outside by using an external JTAG port, and generate, based on a signal received from the JTAG port, a debug signal including an address of the to-be-debugged unit and a debug instruction, where the debug signal is a JTAG port signal based on the JTAG protocol; a signal conversion unit, configured to receive the debug signal that is output from the TAP controller, and convert the debug signal from the JTAG port signal to a bus slave port signal that can access a slave port of the to-be-debugged unit; and a bus, configured to obtain the debug signal that is converted to the bus slave port signal and that is output from the signal conversion unit, and transmit, based on the debug signal, the debug instruction to the to-be-debugged unit indicated by the address of the to-be-debugged unit.

The present disclosure relates to a method wherein a state of an integrated circuit between a first state (e.g., CLOSED), allowing a reading access to the first area of fuse-type non-volatile memory by a processor, and a second state (e.g., OPEN), forbidding the reading access to the memory to the processor, is conditioned to a verification, by a finite state machine, of values of a first fuse word of the memory, representative of a number of transitions to the first state and of a second fuse word of the memory, representative of a number of transitions to the second state.

According to an embodiment, a method for testing a triple-voting flop (TVF) is provided. The method includes providing a first and a second scan enable signal by a control circuit to, respectively, a first scan flip-flop and a third scan flip-flop of the TVF; receiving a third scan enable signal at the second scan flip-flop of the TVF; providing a scan input signal to the first scan flip-flop, the second scan flip-flop, and the third scan flip-flop; controlling the first scan enable signal, the second scan enable signal, and the third scan enable signal; receiving, at an output of the TVF, a scan output signal; and determining whether the TVF suffers from a fault based on the scan output signal and the controlling of the first scan enable signal, the second scan enable signal, and the third scan enable signal.

An integrated circuit has a first scan cell segment, a second scan cell segment connected to one or more hidden content, and a scan cell circuit connected to the first scan cell segment and the second scan cell segment. The scan cell circuit alternatively provides access to the first scan cell segment and the second scan cell segment based on a state of the scan cell circuit.

An electronic system, a system diagnostic circuit, and an operation method thereof are provided. The system diagnostic circuit includes a data register circuit, an instruction register circuit, a diagnostic controller circuit, a control register circuit, and a detect circuit. The diagnostic controller circuit determines to transmit test data to the instruction register circuit or the data register circuit according to an operating state. The detect circuit update the control register circuit when the first test data transmitted to the data register circuit meets a predefined pattern.

A trusted boot device secures JTAG scan chains of integrated circuit components on a circuit card assembly without necessarily modifying the integrated circuit components. Component JTAG port I/O scan chain signal pins are independently routed to FPGA fabric on the trusted boot device. The trusted boot device monitors the JTAG paths and triggers a security event if unauthorized activity is detected on a JTAG path. JTAG paths on the secure trusted boot device are latch disabled by default and upon detection of a security event. JTAG paths are only enabled for a predefined length of time. To prevent JTAG access when protected data is exposed, a watchdog timer latch disables the JTAG paths when the predefined time has expired and may trigger a security event if activity is detected after the time has expired. A power cycle is then used to re-enable authenticated JTAG enable requests.

Some embodiments include a method for processing a scan chain in an integrated circuit, the method comprising receiving, in the integrated circuit, the scan chain, wherein the scan chain includes a secret key pattern; separating the secret key pattern from the scan chain; storing the scan chain in a first plurality of latches; storing the secret key pattern in a second plurality of latches; comparing the secret key pattern to a reference key pattern, the reference key pattern stored in a third plurality of latches; determining, based on the comparing the secret key pattern to the reference key pattern, that the secret key pattern does not match the reference key pattern; and generating a signal indicating that the secret key pattern does not match the reference key pattern.

A scan test circuit includes a scan chain formed of a plurality of sub-scan chains, an input distribution circuit, and an output compression circuit. With the use of a bypass circuit, a plurality of sub-scan chains are formed in a compression scan mode by connecting scan cell circuits of a high confidentiality-requiring circuit among a plurality of scan cell circuits included in an internal circuit, and a plurality of sub-scan chains are formed in a non-compression scan mode by bypassing the scan cell circuits of the high confidentiality-requiring circuit.

A trusted boot device secures JTAG scan chains of integrated circuit components on a circuit card assembly without necessarily modifying the integrated circuit components. Component JTAG port I/O scan chain signal pins are independently routed to FPGA fabric on the trusted boot device. The trusted boot device monitors the JTAG paths and triggers a security event if unauthorized activity is detected on a JTAG path. JTAG paths on the secure trusted boot device are latch disabled by default and upon detection of a security event. JTAG paths are only enabled for a predefined length of time. To prevent JTAG access when protected data is exposed, a watchdog timer latch disables the JTAG paths when the predefined time has expired and may trigger a security event if activity is detected after the time has expired. A power cycle is then used to re-enable authenticated JTAG enable requests.

A system on chip (SoC) is provided. The system on chip includes a multiprocessor that includes multiple processors, a debugging controller that includes a debug port and retention logic configured to store an authentication result of a secure joint test action group system, and a power management unit configured to manage power supplied to the multiprocessor and the debugging controller. The power management unit changes the debug port and the retention logic into an alive power domain in response to a debugging request signal.