An array substrate includes a gate layer, a first insulating layer, a channel layer, a source-drain layer, a second insulating layer, and a common electrode layer that are sequentially stacked, wherein the second insulating lay is provided with via holes formed therein; and the source-drain layer includes a plurality of sources, a plurality of drains, a plurality of data lines and a plurality of common electrode signal lines. The common electrode signal line includes a plurality of common electrode signal line segments, each of the common electrode signal line segments passes through at least one sub-pixel row, and each of the common electrode signal line segments is connected to the common electrode layer through the via hole.

The liquid crystal display device includes: a TFT substrate including scanning lines extending in a first direction and being arranged in a second direction, video signal lines extending in the second direction and being arranged in the first direction, pixel electrodes arranged in regions surrounded by the scanning lines and the video signal lines, and common electrodes formed with an insulating film arranged between the common electrodes and the pixel electrodes; a counter substrate opposed to the TFT substrate; and a liquid crystal. The first common electrode extends between the first and second scanning lines in the first direction, and the second common electrode extends between the second and third scanning lines in the first direction. The first and second common electrodes are electrically connected by a bridge. The bridge covers the first video signal line without covering the second video signal line, when seen in a plan view.

A liquid crystal display device having an outer shape of a display region formed other than a rectangle. A driver for supplying a video signal is disposed outside the display region. A selector with selector TFT is disposed between the display region and the driver. A video signal line is disposed between the driver and the selector, and a drain line is disposed between the selector and the display region. A scanning circuit for supplying a scanning signal to the scanning line is disposed outside the display region. The selector is disposed between the scanning line and the display region, and covered with ITO as the common electrode. The common bus wiring is disposed outside the selector.

In a display system, a source drive circuit outputs a source signal. Multiple switching elements are respectively connected between multiple source lines and the source drive circuit, and each switching element outputs a source signal output from the source drive circuit to a source line in an ON state and stops the output of the source signal to the source line in an OFF state. A switching circuit supplies multiple pulse signals to the multiple switching elements. A CPU determines pulse widths of the multiple pulse signals. The pulse widths of the multiple pulse signals are determined such that each of the pulse widths of the multiple pulse signals is longer than or equal to a charging time of a pixel electrode and such that the sum of the pulse widths of the multiple pulse signals is shorter than or equal to a horizontal synchronization period.

The present application provides an array substrate, a manufacturing method of the array substrate, and a liquid crystal display panel. The array substrate includes first common wirings disposed in a same layer as gate wirings and formed as discontinuous segments, and second common wirings disposed in a same layer as source/drain wirings. The first common wirings are electrically connected to the second common wirings. More openings are provided between the gate wirings and the first common wirings formed as discontinuous segments for a flow of an etchant, so that the first common wirings and the gate wirings are prevented from being formed too thin or broken due to an accumulation of the etchant.

A pixel unit includes: a first insulating layer; a first pixel electrode located on a first side of the first insulating layer and including a plurality of first electrode strips; a common electrode located on the first side of the first insulating layer and including a plurality of second electrode strips, the second electrode strips and the first electrode strips being sequentially and alternately arranged in a first direction, and slits each being disposed between a second electrode strip in the second electrode strips and a first electrode strip in the first electrode strips that are adjacent to each other; and a second pixel electrode located on a second side of the first insulating layer. The second side of the first insulating to layer is opposite to the first side of the first insulating layer. The second pixel electrode is overlapped with at least a region where the slits are located.

A high-resolution display system is provided. A display system with high display quality is provided. The display system includes a processing unit and a display unit. A first image signal is supplied to the processing unit. The processing unit has a function of generating a second image signal by using the first image signal. The processing unit has a function of generating a correction signal. The display unit includes a pixel. The pixel includes a display element and a memory circuit. The second image signal and the correction signal are supplied to the pixel. The memory circuit has a function of retaining the correction signal.

Embodiments of the present disclosure provides an array substrate and a manufacturing method thereof, a display panel. The array substrate includes: a base; a pixel electrode and a thin film transistor disposed on the base; a passivation layer covering the thin film transistor and the pixel electrode, the passivation layer being provided with a transferring through hole that simultaneously exposes the pixel electrode and a drain electrode or a source electrode of the thin film transistor; a connection electrode disposed on the passivation layer and at the transferring through hole, the connection electrode connected with the pixel electrode, and the drain electrode or the source electrode through the transferring through hole.

The liquid crystal panel of the present invention sequentially includes: a first substrate including a first electrode; a first alignment film; a liquid crystal layer containing liquid crystal molecules having a positive anisotropy of dielectric constant; a second alignment film; and a second substrate including a second electrode, the liquid crystal molecules being homogeneously aligned with no voltage applied between the first electrode and the second electrode, a polar anchoring energy 2EA and an azimuthal anchoring energy 2EB of the second alignment film being smaller than a polar anchoring energy 1EA and an azimuthal anchoring energy 1EB of the first alignment film, respectively, the polar anchoring energy 2EA of the second alignment film being not greater than the azimuthal anchoring energy 2EB of the second alignment film.

A LCD device having a large pixel holding capacitance includes opposedly facing first and second substrates, and liquid crystal between them. The first substrate includes a video signal line, a pixel electrode, a thin film transistor having a first electrode connected to the video signal line and a second electrode connected to the pixel electrode, a first silicon nitride film formed above the second electrode, an organic insulation film above the first silicon nitride film, a capacitance electrode above the organic insulation film, and a second silicon nitride film above the capacitance electrode and below the pixel electrode. A contact hole etched in both the first and second silicon nitride films connects the second electrode and the pixel electrode to each other. A holding capacitance is formed by the pixel electrode, the second silicon nitride film and the capacitance electrode.