Disclosed are an array substrate and a method for manufacturing the same. The array substrate includes a transmission gate structure having an upper thin film transistor and a lower thin film transistor. An active layer of the lower TFT is the first active layer, and an active layer of the upper TFT is the second active layer. The first active layer and the second active layer are provided on two sides of a source and drain layer, respectively, and share source and drain electrodes. Compared with the prior art, such structure is simpler, and furthermore it facilitates simplification of a manufacturing process of the transmission gate structure and improves a success rate of preparation thereof.

The invention discloses an array substrate, a display panel, and a display device, where at least one control capacitor is added to a pixel zone, and the control capacitor has a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent transistors, so that when an active gate scan signal is stopped from being loaded on a gate line, the potential of the second electrode of the control capacitor is controlled to be kept at the potential of data signal loaded on a data line, to thereby lower the difference in voltage between the source and the drain of a transistor associated with the second electrode of the control capacitor so as to keep the potential at a connection point of the transistor with a storage capacitor to be the potential of a data signal loaded on the data line.

To provide a circuit used for a shift register or the like. The basic configuration includes first to fourth transistors and four wirings. The power supply potential VDD is supplied to the first wiring and the power supply potential VSS is supplied to the second wiring. A binary digital signal is supplied to each of the third wiring and the fourth wiring. An H level of the digital signal is equal to the power supply potential VDD, and an L level of the digital signal is equal to the power supply potential VSS. There are four combinations of the potentials of the third wiring and the fourth wiring. Each of the first transistor to the fourth transistor can be turned off by any combination of the potentials. That is, since there is no transistor that is constantly on, deterioration of the characteristics of the transistors can be suppressed.

A liquid crystal display device includes a first substrate spaced from a second substrate, a liquid crystal layer between the first and second substrates, a gate line, a data line, a first sub-pixel electrode, and a second sub-pixel electrode on the first substrate. The display device also includes a first switch and a second switch. The first switch is connected to the gate line, the data line, and the first sub-pixel electrode. The second switch is connected to the gate line, the data line, and the second sub-pixel electrode. The second switch includes a first gate electrode connected to the gate line and a second gate electrode not connected to the gate line.

The present invention provides a manufacture method of a Low Temperature Poly-silicon array substrate. A halftone mask is utilized to realize the pattern process to the polysilicon layer and the N type heavy doping process of the polysilicon section of the NMOS region. In comparison with prior art, one mask is eliminated, and thus, the production cost is reduced, and the manufactured Low Temperature Poly-silicon array substrate possesses fine electronic property.

The invention discloses an array substrate, a display panel, and a display device, where at least one control capacitor is added to a pixel zone, and the control capacitor has a first electrode at a fixed potential, and a second electrode at the same potential as a node between two adjacent transistors, so that when an active gate scan signal is stopped from being loaded on a gate line, the potential of the second electrode of the control capacitor is controlled to be kept at the potential of data signal loaded on a data line, to thereby lower the difference in voltage between the source and the drain of a transistor associated with the second electrode of the control capacitor so as to keep the potential at a connection point of the transistor with a storage capacitor to be the potential of a data signal loaded on the data line.

The present application provides a display panel, a fabrication method of a display panel, and a display device. The display panel includes a transparent display panel, and a dimming panel comprising a plurality of pixels for emitting light and is arranged on a side of the transparent display panel. The dimming panel includes an electrochromic layer, an electrolyte layer, and an ion storage layer stacked in sequence. The electrochromic layer and the ion storage layer includes a porous structure, and the dimming panel further includes a first transparent electrode layer disposed on a side of the electrochromic layer away from the electrolyte layer, and the first transparent electrode layer is patterned and disposed corresponding to each pixel.

According to one embodiment, a liquid crystal display device includes a first substrate including a semiconductor layer including a first extension portion and a second extension portion, a gate line, a first common electrode opposed to at least the second extension portion, a source line extending above the second extension portion, a pixel electrode including a main pixel electrode, a second common electrode including a second main common electrode opposed to the source line, and a first alignment film.

A novel input/output device that is highly convenient or reliable, or a novel data processor and a novel semiconductor device are provided. The inventors have devised a structure in which a display portion and an input portion are included; the display portion includes a first display element, a first conductive film electrically connected to the first display element, a second conductive film including a region overlapping with the first conductive film, an insulating film including a region between the second conductive film and the first conductive film, a pixel circuit electrically connected to the second conductive film, and a second display element electrically connected to the pixel circuit; the insulating film includes an opening; and the second conductive film is electrically connected to the first conductive film through the opening. The input portion has a function of sensing an object that approaches a region overlapping with the display portion.

A display device includes a substrate, a gate line connected to a gate driver, a reference voltage line, a data line crossing the gate line and the reference voltage line, a first thin film transistor including a first drain electrode and connected to the gate line and the data line, a second thin film transistor including a second drain electrode, a third thin film transistor connected to the gate line, the reference voltage line, and the second thin film transistor, and a pixel electrode including a first sub-pixel electrode connected to the first thin film transistor and a second sub-pixel electrode connected to the second thin film transistor. The first drain electrode overlaps the reference voltage line, and an area of a region in which the first drain electrode and the reference voltage line overlap each other increases in a direction toward the gate driver.