A liquid crystal display device comprising: a substrate; a gate line that is disposed on the substrate and extends in a first direction; a first insulating film that is disposed on the gate line; a semiconductor pattern that is disposed on the first insulating film; a first transparent electrode that is disposed on the semiconductor pattern, and has a first electrode and a second electrode being spaced apart from each other; a second insulating film that is disposed on the first transparent electrode and partially exposes the first electrode; a data line disposed on the second insulating film and extends in a second direction different from the first direction; a second transparent electrode that is disposed on the second insulating film and at least partially overlaps the second electrode; and a connecting electrode in direct contact with a portion of the exposed first electrode and the data line.

In a transistor substrate of a display device, a plurality of signal lines to which any one of drive signals of a gate signal and a video signal is supplied include a plurality of first signal lines to which the drive signal is supplied. The first signal line is connected to a driving driver, and is formed in an edge region positioned between an end portion of a substrate and a pixel region and in the pixel region. The first signal line is formed to pass through a first wiring formed in a first layer from a second wiring formed in a second layer in the edge region.

An object of the present invention is to suppress deterioration of display quality due to difference in wiring resistance and capacitance between the layers in a display device having a layered wiring structure. In a display device having a layered wiring structure of P layers, and employing a Q-column reversal driving method in which a polarity of a video signal is reversed every Q source bus lines (SL), the plurality of source bus lines SL are wired to the plurality of layers such that taking source bus lines (SL) of a number equal to a double of a least common multiple of P and Q as one group, the number of source bus lines (SL) to which positive video signals are applied matches the number of source bus lines (SL) to which negative video signals are applied in each of the layers in each of horizontal scanning periods.

A display device with high design flexibility is provided. The display device includes a display element, a touch sensor, and a transistor between two flexible substrates. An external electrode that supplies a signal to the display element and an external electrode that supplies a signal to the touch sensor are connected from the same surface of one of the substrates.

A display panel includes a display region and a non-display region. The display region includes a first display region and at least one second display region. The first display region at least partially surrounds the at least one second display region. Each second display region of the at least one second display region includes at least two semi-transparent regions and a spacing region disposed between adjacent semi-transparent regions. The display region is provided with a plurality of sub-pixels and pixel driving circuits electrically connected to the plurality of sub-pixels. Pixel driving circuits electrically connected to the sub-pixels in each semi-transparent region of the at least two semi-transparent regions are at least partially disposed in the first display region and the spacing region.

The present disclosure provides an array substrate. The array substrate includes a plurality of thin film transistors configured in an array arrangement, a plurality of common electrodes, a plurality of mutually insulated pixel electrodes coupled to the common electrodes, and a plurality of metal pads coupled to the common electrodes and configured in a layer different from the common electrodes or the pixel electrodes. The metal pads are electrically connected to drain electrodes of the thin film transistors and pixel electrodes. An orthogonal projection of a metal pad on the array substrate overlaps with at least a portion of an orthogonal projection of a corresponding common electrode on the array substrate.

The present application provides an array substrate and a display panel. The array substrate includes a substrate and a thin film transistor layer. The thin film transistor layer includes a first metal layer and a second metal layer, the first metal layer includes at least one first metal trace, the second metal layer includes at least one second metal trace, the thin film transistor layer includes a trace crossover area, a barrier layer is disposed between the first metal layer and the second metal layer, and the barrier layer at least covers the trace crossover area.

An active matrix substrate includes a gate metal layer, a source metal layer, an interlayer insulating layer, a first transparent conductive layer and second transparent conductive layer formed on or above the interlayer insulating layer, and a lower metal layer formed below the gate metal layer. The lower metal layer includes a plurality of CS bus lines each extending in a column direction and not overlapping a plurality of source bus lines. Each of the plurality of pixels has a drain extension section extending from a drain electrode, a first transparent electrode, a second transparent electrode connected to the drain extension section, and an auxiliary capacitor electrode that includes the lower metal layer and/or the gate metal layer, is electrically connected to at least any one of the plurality of CS bus lines, and overlaps the drain extension section when viewed in a normal direction of the substrate.

An array substrate including a substrate, a plurality of fan-out traces and a plurality of bonding terminals. The substrate includes a display area and a non-display area surrounding the display area. The fan-out traces and the bonding terminals are disposed in the non-display area. The bonding terminals are spaced apart from each other. First ends of the fan-out traces are respectively electrically connected to the bonding terminals. Second ends of the fan-out traces are electrically connected to the display area. The fan-out traces include a plurality of first fan-out traces and a plurality of second fan-out traces. The first fan-out traces are formed by a first metal layer. The second fan-out traces are formed by a second metal layer. An insulating layer is provided between the first metal layer and the second metal layer. The first fan-out traces and the second fan-out traces are partially overlapped.

The preset disclosure provides an array substrate and a method for manufacturing the same, a display panel and a display device. The array substrate includes: a base substrate; data lines and pixel electrodes located on the base substrate, and a light shielding structure located on a side of the data lines close to the base substrate, orthographic projections of the gaps on the base substrate are located within an orthographic projection of the light shielding structure on the base substrate, and the light shielding structure includes a metal layer and a first transparent layer located on a side of the metal layer away from the base substrate.