According to one embodiment, a liquid crystal display device includes a first substrate includes an insulating substrate, an organic insulating film including a first upper surface and a second upper surface, a step being created by a height difference between the first upper surface and the second upper surface, a common electrode located on the first upper surface, a pixel electrode located on the second upper surface, and a first alignment film which covers the common electrode and the pixel electrode, a second substrate includes a second alignment film opposed to the first alignment film, and a liquid crystal layer held between the first alignment film and the second alignment film.

A display device includes a display panel, a timing controller, a first source driver, and a second source driver. The display panel includes a first pixel, a second pixel and a plurality of data lines included in a pixel column. A first data line is connected to the first pixel, and a second data line is connected to the second pixel. The timing controller generates a pattern inversion control signal by detecting a predetermined image pattern from input data. The first source driver is connected to the first and third data lines, and replaces a first channel data corresponding to the first data line with a third channel data corresponding to the third data line in response to the pattern inversion control signal. Similarly, the second source driver replaces a second channel data corresponding to the second data line with a fourth channel data corresponding to the fourth data line.

A thin film transistor array panel includes a substrate, a gate line and a gate pad disposed on the substrate, a gate insulating layer disposed on the gate line and the gate pad, a data line and a data pad disposed on the gate insulating layer, an organic layer disposed on the data line and the data pad, and a connecting member disposed on one of the gate pad and the data pad, in which the organic layer includes a first portion overlapping the connecting member and a second portion not overlapping the connecting member, and a height of the first portion of the organic layer is greater than a height of the second portion of the organic layer.

It is an object of the present invention to form a pixel electrode and a metal film using one resist mask in manufacturing a stacked structure by forming the metal film over the pixel electrode. A conductive film to be a pixel electrode and a metal film are stacked. A resist pattern having a thick region and a region thinner than the thick region is formed over the metal film using an exposure mask having a semi light-transmitting portion. The pixel electrode, and the metal film formed over part of the pixel electrode to be in contact therewith are formed using the resist pattern. Accordingly, a pixel electrode and a metal film can be formed using one resist mask.

In an IPS-mode liquid crystal display device, the area of a terminal portion is decreased. A liquid crystal display device includes a TFT substrate and a counter substrate attached to the TFT substrate with a sealing material, and includes a display region and a terminal portion formed on the TFT substrate. A shielding transparent conductive film is formed on the outer side of the counter substrate. On the terminal portion, an earth pad formed with a transparent conductive film is formed on an organic passivation film. The shielding transparent conductive film is connected to the earth pad through a conductor. Below organic passivation film of the terminal portion, a wire is formed.

A first interlayer insulating film is arranged on a gate line and a source line. A first common electrode includes a first sub-common electrode extending in the first direction on the first interlayer insulating film and facing the gate line. A second interlayer insulating film covers the first common electrode. A pixel electrode includes a first main pixel electrode extending in the second direction on the second interlayer insulating film. A second common electrode includes a second sub-common electrode and a second main common electrode and set to the same potential as the first common electrode. The second sub-common electrode extends on the second interlayer insulating film in the first direction so as to face the first sub-common electrode, and is cut out on a straight line along which the first main pixel electrode extends. The second main common electrode extends in the second direction facing the source line.

The present disclosure discloses a panel structure of flat displays and the manufacturing method thereof. The panel structure includes a first signal line, a second signal line, a transparent conductive film, and a scanning line. The transparent conductive film includes a first branch, a second branch, and a third branch. A first end of the first branch and a first end of the second branch are connected by a predetermined first angle, and a second end of the second branch and a first end of the third branch are connected by a predetermined second angle. The first branch, the second branch, and the third branch form the arch-shaped frame. The first signal line connects to the second end of the first branch, and the second signal line connects to the second end of the third branch. The scanning line passes through the arch-shaped frame along a first direction.

An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.

An active matrix substrate (100A) includes a TFT (20), a scanning line (11) substantially parallel to a first direction, a signal line (12) substantially parallel to a second direction which is orthogonal to the first direction, a first interlayer insulating layer (16) covering the TFT, a lower layer electrode (17) provided on the first interlayer insulating layer, a dielectric layer (18) provided on the lower layer electrode, and an upper layer electrode (19) overlapping at least a portion of the lower layer electrode via the dielectric layer. A first contact hole (31) includes a first aperture (16a) formed in the first interlayer insulating layer and a second aperture (18a) formed in the dielectric layer. A width of the first aperture along one of the first direction and the second direction is smaller than a width of the second aperture along the one direction. A portion of the contour of the second aperture is located inside the contour of the first aperture, and the contour of the second aperture is not rectangular. The area of the portion of the second aperture not overlapping the first aperture is smaller than that in an imaginary case where the contour of the second aperture is rectangular.

An array substrate, a display panel and a display device are disclosed. The array substrate includes a display region and a non-display region around the display region, and further includes: a first leading wire extending from the non-display region to the display region and a second leading wire extending from the non-display region to the display region. The first leading wire is between a first signal line and a first fan-out line and electrically connects the first signal line and the first fan-out line, and the second leading wire is between a second signal line and a second fan-out line and electrically connects the second signal line and the second fan-out line. The first leading wire and the second leading wire are in different layers.