The present application discloses a display panel, a manufacture method and a display apparatus. The display panel includes a first substrate; the first substrate includes a base, a first metal layer, an insulating layer and a second metal layer; the second metal layer includes horizontal zones and oblique zones; each of the oblique zones is inclined from a first height to a second height; the first height is greater than the second height; a thickness of each of the horizontal zones of the second metal layer is greater than a thickness of each of the oblique zones of the second metal layer; and a width of each of the oblique zones of the second metal layer is greater than a width of each of the horizontal zones of the second metal layer.

A display panel, a manufacturing method thereof, and a display apparatus are provided. The display panel includes a first display region; a plurality of first pixel units, wherein each of the first pixel units includes a light-transmitting region and a light-emitting device; a first substrate including a first portion for mounting the light-emitting device. A plurality of electrodes of the light-emitting device are electrically connected to a first driving circuit by an electric connecting wire, so that the under-screen sensing technique overlapping the optical display in space of the display panel is achieved, and a thickness of the display panel is reduced.

An array substrate, a method for fabricating the same, and a display panel are provided. The array substrate includes a first metal layer, a first insulating layer, a second metal layer, a second insulating layer, and a third metal layer. The first metal layer includes a first data line and a first vertical scan line. The second metal layer includes a horizontal scan line. The third metal layer includes a second data line and a second vertical scan line. The second data line is connected to the first data line through a first via hole. The second vertical scan line is connected to the first vertical scan line through a second via hole. The second vertical scan line is connected to the horizontal scan line through a third via hole. The first via hole, the second via hole, and the third via hole are formed by a same manufacturing process.

In a liquid crystal display device, a second substrate includes a detection electrode of a touch panel, pixels include pixel electrodes and counter electrodes, the counter electrodes are divided into a plurality of blocks, the counter electrodes of the divided blocks are provided in common to the pixels on a plurality of display lines being side by side, the counter electrodes of the divided blocks are used as scanning electrodes of the touch panel as well, the liquid crystal display device includes a semiconductor chip configured to supply a counter voltage and a touch panel scanning voltage to the counter electrodes of the divided blocks, the semiconductor chip includes a first terminal group formed on a side of a display area side configured by the plurality of pixels.

According to one embodiment, a display device includes a semiconductor layer, a first insulating layer, a gate electrode, a second insulating layer and a plurality of transparent conductive layers. The transparent conductive layers include a pixel electrode, a first conductive layer and a second conductive layer. The pixel electrode is in contact with the second conductive layer. The second conductive layer is in contact with the first conductive layer. The first conductive layer is brought into contact with a second region of the semiconductor layer through a first contact hole.

A dual-gate array substrate includes: a plurality of gate lines arranged in a first direction and each extended in a second direction that is perpendicular to the first direction; a plurality of primary signal lines and secondary signal lines arranged alternately in the second direction and extended in the first direction; and a plurality of pixel units. The primary signal lines are connected to a drive unit, and connected respectively to the pixel units that are adjacent thereto. Common electrodes include a plurality of main electrodes and a plurality of branching electrodes. An orthographic projection of the main electrode on the dual-gate array substrate does not overlap with those of corresponding ones, adjacent to the main electrode, of the pixel electrodes and at least covers the primary signal line. Each gate line includes a protrusion protruded in the first direction.

A wiring structure includes a structure body including a pattern, a first conductive layer above the structure body, the first conductive layer having a shape, the shape crossing an edge of a pattern of the structure body and reflecting a step of the edge of the pattern of the structure body, a first insulating layer above the first conductive layer, the first insulating layer having a first opening overlapping the edge of the pattern of the structure body in a plane view, and r is arranged with a second opening in a region overlapping the semiconductor layer in a plane view, a second conductive layer in the first opening, the second conductive layer being connected to the first conductive layer.

An active matrix substrate includes a thin film transistor that includes a gate electrode, a first inorganic insulating film that covers the gate electrode, a second inorganic insulating film that is disposed on the first inorganic insulating film and that has an opening overlapping the gate electrode, a source electrode and a drain electrode disposed on the second inorganic insulating film, and a semiconductor layer that overlaps the gate electrode in an opening of the first inorganic insulating film and that covers the source electrode and the drain electrode. Regarding a surface of the first inorganic insulating film in a first region overlapping the opening of the first inorganic insulating film and a surface in a second region other than the first region, the surfaces being arranged nearer to the second inorganic insulating film, the surface in the first region is lower than the surface in the second region.

Amorphous multi-component metallic films can be used to improve the performance of electronic components such as resistors, diodes, and thin film transistors. Interfacial properties of AMMFs are superior to those of crystalline metal films, and therefore electric fields at the interface of an AMMF and an oxide film are more uniform. An AMMF resistor (AMNR) can be constructed as a three-layer structure including an amorphous metal, a tunneling insulator, and a crystalline metal layer. By modifying the order of the materials, the patterns of the electrodes, and the size and number of overlap areas, the I-V performance characteristics of the AMNR are adjusted. A non-coplanar AMNR has a five-layer structure that includes three metal layers separated by metal oxide tunneling insulator layers, wherein an amorphous metal thin film material is used to fabricate the middle electrodes.

In various embodiments, electronic devices such as thin-film transistors and/or touch-panel displays incorporate bilayer capping layers and/or barrier layers.