The invention provides a thin film transistor (TFT) array substrate, a manufacturing method thereof, and a display panel. The TFT array substrate includes a substrate. A buffer layer and a TFT functional layer are sequentially disposed on the substrate. The TFT functional layer includes an active layer (Active), a gate insulating layer (GI), a gate layer (GE), an interlayer insulating layer (ILD), and a source-drain layer (SD) that are sequentially disposed on the buffer layer. An inorganic insulating layer is disposed on the source-drain layer, and a backside indium tin oxide (BITO) layer, a passivation layer (PV), and a top indium tin oxide (TITO) layer are sequentially disposed on the inorganic insulating layer. The invention provides the TFT array substrate. The TFT array substrate adopts a new functional layer structure design, which can effectively reduce production cost and cycle time of the TFT array substrate.

A display device including: a substrate; a first thin film transistor of polysilicon semiconductor, a second thin film transistor of oxide semiconductor; a first light shading film opposing to the polysilicon semiconductor, and a second light shading film opposing to the oxide semiconductor; a first insulating film, a second insulating film which is constituted from plural insulating films, and a third insulating film superposed in this order; a first through hole penetrating the second insulating film and not penetrating the first insulating film and the third insulating film; a second through hole penetrating the first insulating film and the third insulating film; the first light shading film connects with a first conductive component, a part of the first conductive component exists on the third insulating film, through the second through hole.

An electro-optical device includes a scanning line extending along a first direction and having a light shielding property, a transistor having a semiconductor layer extending along the first direction so as to overlap with the scanning line, a contact hole electrically coupled to the scanning line at a side of a channel region of the semiconductor layer, and an opening provided at a side of a first LDD region and a second LDD region of the semiconductor layer.

A display apparatus includes a substrate including a display area, a non-display area outside the display area, a pad area located in the non-display area, and a bending area between the display area and the pad area. The display apparatus includes a first voltage line having a first main voltage line disposed between the display area and the bending area, and a first connection portion protruding from the first main voltage line, extending toward the pad area, and crossing the bending area. The display apparatus includes a fan-out portion disposed between the display area and the pad area on the substrate and including conductive lines that connect the display area to the pad area, and a strain gauge disposed in the bending area. The strain gauge overlaps the first connection portion of the first voltage line in the bending area.

A display device includes a gate wiring; a source wiring; a pixel electrode; a first transistor that has a first gate electrode having a portion of the gate wiring not overlapping the source wiring, a first source electrode, a first drain electrode connected to the pixel electrode, and a first channel region; a second transistor that has a second gate electrode having a portion of the gate wiring intersecting the source wiring, a second source electrode, a second drain electrode separated from the pixel electrode, and a second channel region; and a connectable portion connectable to the second drain electrode and the pixel electrode.

The present application discloses an array substrate and a display panel. The array substrate includes an underlying substrate and a first color resist layer. The first color resist layer is formed on the underlying substrate to block a channel region. The first color resist layer has at least two color resist layers, and the two color resist layers correspond to different colors and are disposed in a stack-up manner.

According to an embodiment of the present invention, an active matrix substrate (100) includes a display region (DR) defined by a plurality of pixel regions (P) arranged in a matrix and a peripheral region (FR) located around the display region. The active matrix substrate includes a substrate (1), a first TFT (10), and a second TFT (20). The first TFT is supported by the substrate and disposed in the peripheral region. The second TFT is supported by the substrate and disposed in the display region. The first TFT includes a crystalline silicon semiconductor layer (11), which is an active layer. The second TFT includes an oxide semiconductor layer (21), which is an active layer. The first TFT and the second TFT each have a top-gate structure.

A thin-film transistor is disclosed. The thin-film transistor includes a gate electrode disposed on a substrate, an oxide semiconductor layer disposed so as to overlap at least a portion of the gate electrode in the state of being isolated from the gate electrode, a gate insulation film disposed between the gate electrode and the oxide semiconductor layer, a source electrode connected to the oxide semiconductor layer, and a drain electrode connected to the oxide semiconductor layer in the state of being spaced apart from the source electrode, wherein the oxide semiconductor layer includes indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O), the content of indium (In) in the oxide semiconductor layer is greater than the content of gallium (Ga), the content of indium (In) is substantially equal to the content of zinc (Zn), and the content ratio (Sn/In) of tin (Sn) to indium (In) is 0.1 to 0.25.

A semiconductor device with favorable electrical characteristics is provided. A semiconductor device capable of high-voltage driving is provided. A semiconductor device in which a large amount of current can flow is provided. The semiconductor device has a structure including a semiconductor layer, a first insulating layer, a second insulating layer, a metal oxide layer, a conductive layer, and an insulating region. The metal oxide layer is positioned between the first insulating layer and the conductive layer. The insulating region is adjacent to the metal oxide layer and is positioned between the first insulating layer and the conductive layer. The semiconductor layer includes a first region in contact with the first insulating layer and overlapping with the metal oxide layer and the conductive layer with the first insulating layer therebetween, a second region in contact with the first insulating layer and overlapping with the insulating region and the conductive layer with the first insulating layer therebetween, a third region in contact with the first insulating layer, and a fourth region in contact with the second insulating layer. The insulating region shows a different permittivity from the first insulating layer.

A self-capacitive touch display panel, a driving method thereof, and a display device are provided. The self-capacitive touch display panel includes a first substrate including a first base, a touch electrode layer, a driving circuit layer, and a pixel electrode layer, wherein the touch electrode layer is disposed between the first base and the driving circuit layer; a second substrate; and a liquid crystal layer. It realizes integration of a vertically-oriented display panel and a self-capacitive touch scheme, which saves costs, has high sensitivity, and is more suitable for large-sized commercial products.