The present invention provides a low-latency thin film transistor, an array substrate, and a display panel. The low-latency thin film transistor includes a gate, an active layer disposed on a side of the gate, and a source and a drain disposed above the gate, and the source and the drain are respectively connected to the active layer, wherein in a direction perpendicular to the active layer, at least part of an orthographic projection of the drain is located outside an orthographic projection of the gate.

An array substrate includes: a substrate, and a thin film transistor TFT, a first passivation layer and a transparent electrode disposed on the substrate. Only the first passivation layer is disposed between the transparent electrode and an active layer in the TFT. In this way, a film structure of the array substrate is effectively simplified because no organic insulation layer is disposed in the array substrate, thereby simplifying a manufacturing process of the array substrate and reducing the manufacturing cost of the array substrate.

The oxide semiconductor layer is electrically connected to a source electrode or the source bus line within the source opening formed in the lower insulating layer, each wiring line connection section includes a lower conductive portion formed using the first conductive film, the lower insulating layer extending over the lower conductive portion, an oxide connection layer formed using an oxide film the same as the oxide semiconductor layer and electrically connected to the lower conductive portion within the lower opening formed in the lower insulating layer, an insulating layer covering the oxide connection layer, and an upper conductive portion electrically connected to the oxide connection layer within the upper opening formed in the insulating layer, wherein the oxide connection layer includes a region lower in a specific resistance than the channel region of the oxide semiconductor layer.

A touch panel includes a substrate, scan lines, data lines, sub-pixels, a first conductive line, a second conductive line, and a conductive layer. The sub-pixels are arranged in columns along a first direction and arranged in rows along a second direction. Each of the sub-pixels includes an active element and a pixel electrode electrically connected with the active element. The active element is electrically connected with a corresponding scan line and a corresponding data line. The conductive layer overlaps the sub-pixels. The conductive layer includes a first electrode and a second electrode. The first electrode is electrically connected with the first conductive line. The second electrode is electrically connected with the second conductive line. The second electrode is separated from the first electrode. One of the first electrode and the second electrode is a touch electrode, and another one is a common electrode.

To provide a semiconductor device including a narrowed bezel obtained by designing a gate driver circuit. A gate driver of a display device includes a shift register unit, a demultiplexer circuit, and n signal lines. By connecting the n signal lines for transmitting clock signals to one stage of the shift register unit, (n−3) output signals can be output. The larger n becomes, the smaller the rate of signal lines for transmitting clock signals which do not contribute to output becomes; accordingly, the area of the shift register unit part is small compared to a conventional structure in which one stage of a shift register unit outputs one output signal. Therefore, the gate driver circuit can have a narrow bezel.

According to one embodiment, a display device includes a gate line extending in a first direction, first and second source lines crossing the gate line and arranged in the first direction, a first light-shielding layer having first and second openings, and an oxide semiconductor layer crossing the gate line, and in the display device, the first opening and the second opening are arranged in a second direction crossing the first direction between the first source line and the second source line, the gate line is located between the first opening and the second opening, and the oxide semiconductor layer has a first overlapping portion overlapping the first opening.

A device having a stack of layers defining source and pixel conductors at a first level, gate and common conductors at a second level, semiconductor channels between the source and pixel conductors and gate dielectric capacitively coupling the semiconductor channels to the gate conductors. The pixel and common conductors are configured such that, in use, a change in potential difference between the pixel and common conductors in a pixel region induces a change in one or more optical properties of a liquid crystal material in the pixel region.

A display device including a pixel electrode disposed in an opening area; a common electrode of which at least a region is disposed to be overlapped with the pixel electrode; a gate line extending along a first direction in a non-opening area surrounding the opening area and transmitting a gate signal to the pixel electrode; a data line extending along a second direction different from the first direction in the non-opening area, and transmitting a data signal to the pixel electrode; and a dummy line disposed to be overlapped with the data line in the non-opening area and electrically connected to the common electrode.

A novel display panel that is highly convenient or reliable is provided. A pixel circuit includes a first switch, a node, a first capacitor, a second capacitor, and a second switch. The first switch includes a first terminal to which a first signal is supplied and a second terminal electrically connected to the node. The first capacitor includes a first terminal electrically connected to the node. The second capacitor includes a first terminal electrically connected to the node and a second terminal electrically connected to the second switch. The second switch includes a first terminal to which a second signal is supplied and a second terminal electrically connected to the second terminal of the second capacitor. In addition, the second switch has a function of changing from a non-conducting state to a conducting state when the first switch is in a non-conducting state and a function of changing from a conducting state to a non-conducting state when the first switch is in a non-conducting state. The display element performs display on the basis of a potential of the node.

There is provided an array substrate, a manufacturing method therefor, a display panel, and a display device. The array substrate includes: a base substrate, and a gate metal pattern, a gate insulating layer and a source-drain metal pattern which are sequentially disposed on the base substrate. The gate metal pattern includes a signal line and a gate electrode, the signal line is in the peripheral area, the gate insulating layer is provided with a first via hole penetrating the gate insulating layer, the orthogonal projection of the first via hole on the base substrate and the orthogonal projection of the signal line on the base substrate have an overlapping area, the source-drain metal pattern includes a source-drain electrode wire, and the source-drain electrode wire is electrically connected to the signal line through the first via hole. The present disclosure achieves the function of protecting the signal line.