A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

A reference voltage generator includes a voltage generation circuit, an amplifier, a diode unit and a transistor. The voltage generation circuit includes an output terminal for outputting a reference voltage, a first terminal having an operational voltage, and a second terminal. The amplifier includes an input terminal coupled to the first terminal of the voltage generation circuit, an output terminal, a first terminal coupled to a first voltage terminal, and a second terminal. The diode unit includes a first terminal coupled to the second terminal of the amplifier, and a second terminal coupled to the second terminal of the voltage generation circuit and a second voltage terminal. The transistor includes a first terminal coupled to the first terminal of the amplifier, a second terminal coupled to the output terminal of the voltage generation circuit, and a control terminal coupled to the output terminal of the amplifier.

A buffer system may have an output for driving a switched load that changes during periods indicated by a switching signal. The buffer system may operate in a closed loop when the switching signal indicates that a load change is not taking place by comparing a signal indicative of the output of the buffer system with a reference voltage. The buffer system may operate in an open loop when the switching signal indicates that a load change is taking place by not comparing signal indicative of the output of the buffer system with the reference voltage. Both the buffer system and the switched load may be on the same chip.

The disclosure provides a voltage generating device and a calibrating method thereof. The voltage generating device includes a bandgap circuit, a regulator circuit and a calibrating circuit. The bandgap circuit provides a bandgap voltage. The regulator circuit generates an output voltage correspondingly according to the bandgap voltage. In a first stage of a calibration period, the calibrating circuit detects the bandgap voltage, and correspondingly sets a resistance of at least one resistor of the bandgap circuit according to the bandgap voltage. In a second stage of the calibration period, the calibrating circuit detects the output voltage, and correspondingly sets a resistance of at least one resistor of the regulator circuit according to the output voltage.

A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.

An adaptive low-dropout regulator (LDO) having a wide voltage endurance range includes a power supply voltage tracker (P1), a voltage-current converter (101), an error amplifier (201), a current mirror circuit (102), and a dynamic voltage divider (103). One end of the power supply voltage tracker (P1) is connected to a V.sub.dd, the other end thereof is connected to the voltage-current converter (101) connected to an input end of the current mirror circuit (102), and an output end of the current mirror circuit (102) is connected to sources of two input field effect transistors (N3, N4) in the error amplifier (201). Sources of two load field effect transistors (P2, P3) in the error amplifier (201) are connected to the V.sub.dd. Dynamic voltage dividers (103A, 103B) are connected respectively between each of the input field effect transistors (N3, N4) and the corresponding load field effect transistors (P2, P3).

Systems, methods and apparatus for efficient control and biasing of pass devices that include at least one thin pass device and a remaining of thick pass devices. When operated at extreme high and low voltages, the at least one thin pass device maintains operation in its saturation region of operation while the remaining pass devices may be driven into their triode regions of operation. The thin and thick pass devices are arranged in a cascode configuration that includes a plurality of stacked devices. Biasing of the thin and thick cascode devices can be according to a voltage division scheme which protects the devices when the voltage across the stack is high, and provides a skewed voltage division across the stacked devices that promotes a higher gate-to-source voltage of the thick pass devices for a lower R.sub.ON. In one exemplary case, gate length of the at least one thin pass device may be reduced to provide a lower gate-to-source voltage of the thin pass device during operation in the saturation region. An exemplary implementation of an LDO controlling the pass devices for providing RF power to a power amplifier is described.

An adaptive low-dropout regulator (LDO) having a wide voltage endurance range includes a power supply voltage tracker (P1), a voltage-current converter (101), an error amplifier (201), a current mirror circuit (102), and a dynamic voltage divider (103). One end of the power supply voltage tracker (P1) is connected to a V.sub.dd, the other end thereof is connected to the voltage-current converter (101) connected to an input end of the current mirror circuit (102), and an output end of the current mirror circuit (102) is connected to sources of two input field effect transistors (N3, N4) in the error amplifier (201). Sources of two load field effect transistors (P2, P3) in the error amplifier (201) are connected to the V.sub.dd. Dynamic voltage dividers (103A, 103B) are connected respectively between each of the input field effect transistors (N3, N4) and the corresponding load field effect transistors (P2, P3).

A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.

A circuit and method for providing a temperature compensated voltage comprising a voltage regulator circuit configured to provide a regulator voltage, a voltage reference circuit configured to provide a reference voltage, VREF, a comparison circuit configured to provide a control voltage VCTL, and an operational amplifier configured to provide amplification and coupling to said comparison circuit, wherein the voltage can be a high voltage greater than 1.2 V.