A circuit includes a first current source configured to produce a first current in a first current line through a first diode-connected transistor having a voltage drop across the first diode-connected transistor, the first current being proportional to an absolute temperature via a first proportionality factor; a second current source configured to produce a second current in a second current line through a second diode-connected transistor having a voltage drop across the second diode-connected transistor, the second current being proportional to the absolute temperature via a second proportionality factor; a third current source configured to produce a third current in a third current line through a third diode-connected transistor having a voltage drop across the third diode-connected transistor; and a processing network including a sigma-delta analog-to-digital converter, the processing network being coupled to the, the second, and the third diode-connected transistors.

Certain aspects of the present disclosure are generally directed to circuitry and techniques for adjusting an audio signal to avoid undesirable system behavior under low alternating-current (AC) line voltage and high volume conditions. For example, certain aspects provide an apparatus for audio amplification. The apparatus generally includes an amplifier, a supply voltage generation circuit having an input coupled to an input voltage node of the apparatus and an output coupled to a supply voltage terminal of the amplifier, the supply voltage generation circuit having a transformer, a primary winding of the transformer being coupled to the input voltage node, a peak voltage detector circuit configured to detect a peak voltage at a secondary winding of the transformer, and a controller circuit configured to adjust an input audio signal of the amplifier based on the detected peak voltage.

Certain aspects of the present disclosure are generally directed to circuitry and techniques for adjusting an audio signal to avoid undesirable system behavior under low alternating-current (AC) line voltage and high volume conditions. For example, certain aspects provide an apparatus for audio amplification. The apparatus generally includes an amplifier, a supply voltage generation circuit having an input coupled to an input voltage node of the apparatus and an output coupled to a supply voltage terminal of the amplifier, the supply voltage generation circuit having a transformer, a primary winding of the transformer being coupled to the input voltage node, a peak voltage detector circuit configured to detect a peak voltage at a secondary winding of the transformer, and a controller circuit configured to adjust an input audio signal of the amplifier based on the detected peak voltage.

Systems and methods for providing a high performance current source are described. In an example implementation, the current source includes transistors in dual current mirror configuration. The dual mirror configuration employs current feedback to increase the output resistance of the current source while achieving a wide voltage swing.

A current mirror arrangement with a current mirror and a double-base current circulator is disclosed. The current mirror is configured to receive an input current (I.sub.IN) and generate a mirrored current (IM), where IM=K*I.sub.IN. The current circulator, coupled to the current mirror, is configured to convey the mirrored current to an output node of the arrangement. The current circulator is a double-base current circulator and includes a first branch configured to receive a first branch current (I1b), where I1b=m*IM, where m is a positive number less than 1, and further includes a second branch configured to receive a second branch current (I2b), where I2b=(1m)*IM. The first branch includes a cascode of transistors Q3 and Q5, configured to provide I1b to an output node. The second branch includes a transistor Q4 configured to provide I2b to the output node, where it is combined with I1b.

A power amplifier configured to amplify a received input signal, and the power amplifier includes a bias circuit and an output stage circuit. The bias circuit includes a reference voltage circuit and a bias generating circuit. The reference voltage circuit receives the first system voltage and provides a reference voltage according to a first system voltage, and the reference voltage changes as the temperature of the wafer changes. The bias generating circuit receives the second system voltage and the reference voltage, and generates an operating voltage. The output stage circuit is coupled to the bias circuit to receive the operating voltage and the driving current to receive and amplify the input signal. When a chip temperature is changed, the bias generating circuit changes the operating voltage according to the reference voltage, such that the driving current approaches a predetermined value as the chip temperature rises.

A voltage reference circuit comprising: a resistive track having a first force contact and a second force contact, the first and second force contacts configured to pass a current through the resistive track; a first sense contact, a second sense contact and a third sense contact wherein each of the sense contacts are arranged at different positions along the resistive track between the first and second force contacts and the sense contacts arranged to define a first resistor and a second resistor; a first component arrangement comprising a P-N junction which has a temperature dependent voltage bias; a second component arrangement; wherein one or both of the first component arrangement and the second component arrangement provide for a counter-bias voltage, the counter bias voltage for countering the temperature dependent voltage bias of the P-N junction such that the voltage reference circuit is configured to provide a constant output reference voltage.

A current source includes a substrate, a base region of a first doping type formed in the substrate, an emitter region of a second doping type formed in the substrate and surrounding the base region, a first collector region of the second doping type formed in the base region, and at least one second collector region of the second doping type formed in the base region, wherein the emitter region includes a deep-well portion and an extending portion, the deep-well portion situated beneath the base region, the extending portion laterally surrounding the base region, the extending portion joined at its bottom to the deep-well portion, the extending portion being flush at its top with a top surface of the substrate. A method of forming the current source is also disclosed.

This invention provides an accurate current mirror circuit in a low voltage headroom applied to common-anode laser drivers, including a reference current detection unit, a tail current source unit, and a control unit. The reference current detection unit generates a bias voltage and a reference voltage according to a reference current from the reference current source; the tail current source unit receives the bias voltage and generate a mirror current accordingly; the control unit receives the reference voltage and an output voltage corresponding to the mirror current and carry out a feedback regulation to the bias voltage accordingly. In this invention, the reference voltage and the output voltage are locked at same level, and then the bias voltage is mirrored to generate the mirror current outputted to the laser, thus avoiding the problem of inaccurate current output caused by the offset of the control unit in the low voltage headroom.

A current reference circuit includes a native metal oxide semiconductor field effect transistor (MOSFET). The native MOSFET includes a source terminal coupled to ground. The current reference circuit also includes a transistor and an amplifier circuit. The transistor includes a first terminal coupled to a drain terminal of the native MOSFET, a second terminal coupled to a power supply rail, and a third terminal coupled to the drain terminal of the native MOSFET. The amplifier circuit includes an input terminal coupled to the drain terminal of the native MOSFET, and an output terminal coupled to a gate terminal of the native MOSFET.