Techniques for an integrated slew-rate control circuit are provided. In certain examples, an adjustable, integrated slew-rate control circuit for a bypass transistor can provide three decades of adjustability. In an example, a slew-rate control circuit can include a load bypass transistor, a slew-rate control capacitor, electrically coupled between a conduction node of the load bypass transistor and a control node of the load bypass transistor, and a current mirror circuit. The current mirror circuit can include a sense transistor electrically coupled in series with the slew-rate control capacitor and the control node, and a mirror transistor electrically coupled between a power supply and the control node, to selectively provide, to or from the control node, a shunt current that bypasses the slew-rate control capacitor to limit a slew rate of a voltage at the conduction node.

Provided are a semiconductor circuit and a semiconductor system. A semiconductor circuit includes a bandgap reference voltage generation circuit including an operational amplifier to amplify a differential voltage between a first node and a second node; a first startup circuit which receives input of an output signal of the operational amplifier from an output voltage node of the bandgap reference voltage generation circuit and pulls up the second node; and a second startup circuit which pulls down the output voltage node.

Examples of bandgap circuits and elements thereof enable generation of an accurate and stable bandgap reference voltage that is not affected by low current gain. An example circuit includes first and second input transistors, each having an emitter to receive a tail current; first and second core transistors, a collector of each coupled to ground; a first lower leg coupled between a first upper leg and the emitter of the first core transistor at a first current input coupled to the base of the first input transistor; a second lower leg coupled between a second upper leg and the emitter of the second core transistor at a second current input coupled to the base of the second input transistor; and a base resistor coupled between the base and collector of the first core transistor. The input transistor pair has a current density ratio that is the same as that of the core transistor pair.

A bandgap circuit that is area efficient and has a low power consumption. The bandgap circuit includes a voltage generator circuit, and a sample and hold circuit coupled to the voltage generator circuit. The voltage generator circuit includes a pair of transistors each connected in a diode configuration and biased with a respective current source of a plurality of current sources of the voltage generator circuit. During a sample phase, the sample and hold circuit samples a first voltage between a first base and a first emitter of a first transistor of the pair of transistors and a second voltage between a second base and a second emitter of a second transistor of the pair of transistors. During a hold phase subsequent to the sample phase, the sample and hold circuit generates an output voltage as a combination of the sampled first and second voltages.

In accordance with an embodiment, a circuit includes: a trimmable reference current generator having a temperature dependent current output node, the trimmable reference current generator including: a proportional to absolute temperature (PTAT) current generation circuit; a first programmable current scaling circuit coupled to the PTAT current generation circuit and including a first output coupled to the temperature dependent current output node; a constant current generation circuit; a second programmable current scaling circuit coupled to the constant current generation circuit and including a first output coupled to the temperature dependent current output node; and a reference interface circuit having an input coupled to the temperature dependent current output node and an output configured to be coupled to a reference current input of a memory sense amplifier.

Example implementations include a bandgap voltage device with a first current source operatively coupled to a bandgap input node and a bandgap output node and operable to output a first proportional-to-absolute-temperature (PTAT) current, a current mirror including a first bandgap transistor and a second bandgap transistor, and operatively coupled to the bandgap output node, and a second current source operatively coupled to the current mirror and operable to output a second PTAT current. Example implementations also include a bandgap transistor device with a first P+ layer proximate to a center of a planar surface of a transistor device, a first N+ layer at least partially surrounding the first P+ layer along the planar surface, a second P+ layer at least partially surrounding the first N+ layer along the planar surface, a second N+ layer at least partially surrounding the second P+ layer along the planar surface, and a third P+ layer at least partially surrounding the second N+ layer along the planar surface.

A bandgap reference circuit includes an amplifier, a first transistor, a second transistor, a third transistor, a first resistor, and a second resistor. The amplifier is configured to generate a bandgap voltage. The first transistor is coupled to the amplifier, and passes a first PTAT current. The second transistor is coupled to the amplifier, and passes a second PTAT current. The first resistor is coupled to the amplifier and the second transistor, and passes the second PTAT current to the second transistor. The third transistor is coupled to the amplifier, and passes a third PTAT current that bypasses the first resistor and the second transistor. The second resistor is coupled to the first transistor, the second transistor, and the third transistor, and passes the first PTAT current, the second PTAT current, and the third PTAT current.

A bandgap reference circuit includes first through fourth bipolar junction transistors (BJTs). The base and collector of the first BJT are shorted together. The second BJT is coupled to the first BJT via a first resistor. The base of the third BJT is coupled to the base of the first BJT. The base and collector of the fourth BJT are coupled together and also are coupled to the base of the second BJT. A second resistor is coupled to the fourth emitter of the fourth BJT. A third resistor is coupled to the second resistor and to the emitter of the second BJT. An operational amplifier has a first input coupled to the first resistor and the collector of the second BJT, a second input coupled to the emitter of the third BJT and the collector of the fourth BJT, and an output coupled to the collectors of the first and third BJTs.

An integrated circuit device having insulated gate field effect transistors (IGFETs) having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure has been disclosed. The integrated circuit device may include a temperature sensor circuit and core circuitry. The temperature sensor circuit may include at least one portion formed in a region other than the region that the IGFETs are formed as well as at least another portion formed in the region that the IGFETs having a plurality of horizontally disposed channels that can be vertically aligned above a substrate with each channel being surrounded by a gate structure are formed. By forming a portion of the temperature sensor circuit in regions below the IGFETs, an older process technology may be used and device size may be decreased and cost may be reduced.

A circuit includes a first current source configured to produce a first current in a first current line through a first diode-connected transistor having a voltage drop across the first diode-connected transistor, the first current being proportional to an absolute temperature via a first proportionality factor; a second current source configured to produce a second current in a second current line through a second diode-connected transistor having a voltage drop across the second diode-connected transistor, the second current being proportional to the absolute temperature via a second proportionality factor; a third current source configured to produce a third current in a third current line through a third diode-connected transistor having a voltage drop across the third diode-connected transistor; and a processing network including a sigma-delta analog-to-digital converter, the processing network being coupled to the, the second, and the third diode-connected transistors.