Methods, systems and computer program products for computing and summing up multiple products in a single multiplier are provided. Aspects include receiving a first number and a second number, creating partial products of the first number and the second number based on a multiplication of the first number and the second number, and reducing the number of partial products to create an intermediate result. Aspects also include receiving a third number and a fourth number, creating partial products of the third number and the fourth number based on a multiplication of the third number and the fourth number, creating a reduction tree and adding the intermediate result to the reduction tree. Aspects further include reducing the number of partial products in the reduction tree to create a second sum value and a second carry value and adding the second sum value and the second carry value to create a result.

A Full Adder (FA) circuit includes a Carry Output Generation (COG) circuit including a first set of inverter gates to generate inverted input signals, and AND gates connected to the first set of inverter gates to generate a first output signal from the inverted input signals. An OR gate is connected to the AND gates, and a second inverter gate is connected to the OR gate. The OR gate generates a second output signal from the first output signal, and the second inverter gate generates a Carry Output (CO) signal from the second output signal. A Sum Generation (SG) circuit is connected to the COG circuit. The SG circuit includes a first cascaded block of transmission gates to generate an output from the CO signal, and a second cascaded block of transmission gates connected to the output of the first cascaded block of transmission gates to generate an output SUM signal.