This method for monitoring an executable code adapted to be executed on a computer platform, the executable code comprising a sequence of software instructions, is implemented by an electronic device and comprises: acquiring the sequence of software instructions; generating a first modeling structure of an execution path of the sequence from the sequence of instructions, the first structure comprising a plurality of first data groups, each associated with a respective instruction and comprising identifiers of a preceding instruction and a following instruction; calculation of a second modeling structure of an operation of the sequence, the second structure comprising a plurality of second groups of data, each associated with a respective instruction and comprising an indicator of possible belonging to a critical chain, and if necessary, an identifier of an initial instruction of said critical chain; the second structure being created by going through the first groups; a critical chain corresponding to instructions of a same software function and being computed by solving a subgraph problem with degree constraints, each critical chain corresponding to a subgraph, the number of instructions included in each critical chain being less than a predefined number, and an optimization parameter being the number of relationships between the instructions of the respective critical chain, said number of relationships corresponding to a number of arcs in the subgraph; and searching for runtime anomaly/anomalies from critical chain(s) determined via the second structure.

A device includes a data path, a first interface configured to receive a first memory access request from a first peripheral device, and a second interface configured to receive a second memory access request from a second peripheral device. The device further includes an arbiter circuit configured to, in a first clock cycle, a pre-arbitration winner between a first memory access request and a second memory access request based on a first number of credits allocated to a first destination device and a second number of credits allocated to a second destination device. The arbiter circuit is further configured to, in a second clock cycle select a final arbitration winner from among the pre-arbitration winner and a subsequent memory access request based on a comparison of a priority of the pre-arbitration winner and a priority of the subsequent memory access request.

A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.

A system includes a memory, an interface engine, and a master. The memory is configured to store data. The inference engine is configured to receive the data and to perform one or more computation tasks of a machine learning (ML) operation associated with the data. The master is configured to interleave an address associated with memory access transaction for accessing the memory. The master is further configured to provide a content associated with the accessing to the inference engine.

A system comprises a processor coupled to a plurality of memory units. Each of the plurality of memory units includes a request processing unit and a plurality of memory banks. The processor includes a plurality of processing elements and a communication network communicatively connecting the plurality of processing elements to the plurality of memory units. At least a first processing element of the plurality of processing elements includes a control logic unit and a matrix compute engine. The control logic unit is configured to access data from the plurality of memory units using a dynamically programmable distribution scheme.

A device includes a memory bank. The memory bank includes data portions of a first way group. The data portions of the first way group include a data portion of a first way of the first way group and a data portion of a second way of the first way group. The memory bank further includes data portions of a second way group. The device further includes a configuration register and a controller configured to individually allocate, based on one or more settings in the configuration register, the first way and the second way to one of an addressable memory space and a data cache.

A system for calculating. A scratch memory is connected to a plurality of configurable processing elements by a communication fabric including a plurality of configurable nodes. The scratch memory sends out a plurality of streams of data words. Each data word is either a configuration word used to set the configuration of a node or of a processing element, or a data word carrying an operand or a result of a calculation. Each processing element performs operations according to its current configuration and returns the results to the communication fabric, which conveys them back to the scratch memory.

A system on a chip (SoC) includes a plurality of processing cores and a stream switch coupled to two or more of the plurality of processing cores. The stream switch includes a plurality of N multibit input ports, wherein N is a first integer, a plurality of M multibit output ports, wherein M is a second integer, and a plurality of M multibit stream links dedicated to respective output ports of the plurality of M multibit output ports. The M multibit stream links are reconfigurably coupleable at run time to a selectable number of the N multibit input ports, wherein the selectable number is an integer between zero and N.

The objective of the present invention is to prevent a conflict between variable names and unintended overwriting of data when a plurality of programs that define shared variables exist. A compiler device (12) includes: an identifier acquisition part (121a) for acquiring an identifier of a first user program; a shared variable name generation part (121b) for generating a shared variable name that includes a variable name of a shared variable and the identifier; a conversion part (121c) for converting the first user program to machine language; and an address determination part (122a) for determining an address of the shared variable. The address determination part (122a) associates the shared variable name and the address of the shared variable with each other and embeds these in the first user program that has been converted to machine language.

A semiconductor device may include a programmable fabric and a processor. The processor may utilize one or more extension architectures. At least one of these extension architectures may be used to integrate and/or embed the programmable fabric into the processor as part of the processor. Systems and methods for transitioning data between the programmable fabric and the processor associated with different clock domains is described.