Patent classifications
G06F12/0824
CACHE SNOOPING MODE EXTENDING COHERENCE PROTECTION FOR CERTAIN REQUESTS
A cache memory includes a data array, a directory of contents of the data array that specifies coherence state information, and snoop logic that processes operations snooped from a system fabric by reference to the data array and the directory. The snoop logic, responsive to snooping on the system fabric a request of a flush or clean memory access operation of an initiating coherence participant, determines whether the directory indicates the cache memory has coherence ownership of a target address of the request. Based on determining the directory indicates the cache memory has coherence ownership of the target address, the snoop logic provides a coherence response to the request that causes coherence ownership of the target address to be transferred to the initiating coherence participant, such that the initiating coherence participant can protect the target address against conflicting requests.
IN-MEMORY LIGHTWEIGHT MEMORY COHERENCE PROTOCOL
A system includes a plurality of host processors and a plurality of HMC devices configured as a distributed shared memory for the host processors. An HMC device includes a plurality of integrated circuit memory die including at least a first memory die arranged on top of a second memory die and at least a portion of the memory of the memory die is mapped to include at least a portion of a memory coherence directory; and a logic base die including at least one memory controller configured to manage three-dimensional (3D) access to memory of the plurality of memory die by at least one second device, and logic circuitry configured to determine memory coherence state information for data stored in the memory of the plurality of memory die, communicate information regarding the access to memory, and include the memory coherence information in the communicated information.
Distributed directory of named data elements in coordination namespace
An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.
KEY-VALUE STORAGE DEVICE AND SYSTEM INCLUDING THE SAME
A data storage device includes a nonvolatile memory device including a key storage area and a value storage area; and a first control circuit configured to control storing a value in the value storage area, and storing a key corresponding to the value with address information of a value in the key storage area according to a key-value (KV) command.
HOST-BASED READ PERFORMANCE OPTIMIZATION OF A CONTENT ADDRESSABLE STORAGE SYSTEM
An apparatus in one embodiment comprises at least one processing device comprising a processor coupled to a memory, with the processing device being configured to maintain a content-based signature cache for a plurality of data pages. For each of a plurality of read operations to be directed to a distributed content addressable storage (CAS) system, the processing device determines if a data page targeted by the read operation has a corresponding content-based signature in the content-based signature cache. Responsive to the data page having a content-based signature in the content-based signature cache, the processing device identifies a particular storage node that stores the data page in the distributed CAS system, and directs the read operation to the identified storage node using the content-based signature to specify the data page targeted by the read operation. The processing device illustratively comprises a host device coupled to the CAS system over a network.
Domain aware data migration in coherent heterogenous systems
Embodiments disclosed herein provide a domain aware data migration scheme between processing elements, memory, and various caches in a CC-NUMA system. The scheme creates domain awareness in data migration operations, such as Direct Cache Transfer (DCT) operation, stashing operation, and in the allocation of policies of snoop filters and private, shared, or inline caches. The scheme defines a hardware-software interface to communicate locality information (also referred herein as affinity information or proximity information) and subsequent hardware behavior for optimal data migration, thus overcoming traditional CC-NUMA limitations.
METHOD, DEVICE, AND STORAGE MEDIUM FOR RETRIEVING SAMPLES
The present disclosure relates to a method, apparatus, device, storage medium, and program for retrieving samples. The method comprises: shuffling a plurality of data blocks in a dataset, wherein each of the plurality of data blocks includes a plurality of samples; dividing the shuffled plurality of data blocks into a plurality of processing batches; shuffling a plurality of samples in a first processing batch among the plurality of processing batches, and obtaining a sample retrieving order corresponding to the first processing batch; and retrieving samples in the sample retrieving order corresponding to the first processing batch, for the first processing batch.
HOME AGENT BASED CACHE TRANSFER ACCELERATION SCHEME
Systems, apparatuses, and methods for implementing a speculative probe mechanism are disclosed. A system includes at least multiple processing nodes, a probe filter, and a coherent slave. The coherent slave includes an early probe cache to cache recent lookups to the probe filter. The early probe cache includes entries for regions of memory, wherein a region includes a plurality of cache lines. The coherent slave performs parallel lookups to the probe filter and the early probe cache responsive to receiving a memory request. An early probe is sent to a first processing node responsive to determining that a lookup to the early probe cache hits on a first entry identifying the first processing node as an owner of a first region targeted by the memory request and responsive to determining that a confidence indicator of the first entry is greater than a threshold.
Coordination namespace processing
An approach is described that accesses data in a shared memory that is shared amongst nodes that include a local node and remote nodes. The local node receives a name corresponding to a named data element in a Coordination Namespace, the Coordination Namespace having been created in a memory distributed amongst the nodes. A hash function is applied to at least a portion of the name with a result of the hash function being a natural node indicator. Data corresponding to the named data element is requested from a natural node identified by the indicator. Based on the request, a response is received from the natural node.
ADJUSTING INSERTION POINTS USED TO DETERMINE LOCATIONS IN A CACHE LIST AT WHICH TO INDICATE TRACKS BASED ON NUMBER OF TRACKS ADDED AT INSERTION POINTS
Provide a computer program product, system, and method for adjusting insertion points used to determine locations in a cache list at which to indicate tracks based on number of tracks added at insertion points. There are a plurality of insertion points to a cache list for the cache having a least recently used (LRU) end and a most recently used (MRU) end. Each insertion point of the insertion points identifies a track in the cache list. A plurality of tracks are indicated at positions in the cache list with respect to insertion points. For each track indicated at an insertion point of the insertion points, at least one insertion point counter for at least one insertion point with respect to the insertion point at which the track is indicated is incremented. A plurality of the insertion points are adjusted to point to different tracks in the cache list based on insertion point counters for the insertion points.