An approach is disclosed that tracks memory transactions by a node. The approach establishes a transaction processing state corresponding to common virtual addresses accessed by a processing threads. Transactions are executed by the threads. A selected transaction is allowed to complete. In response to detecting a conflict in the transaction processing state, completion of a non-selected transaction is inhibited.

An approach is described that provides a distributed directory structure within a storage of an information handling system (a local node). A request is received with the request corresponding to a shared virtual address. The shared virtual address that is shared amongst a number of nodes that includes the local node and some remote nodes. A Global Address Space Directory (GASD) is retrieved that corresponds to a global virtual address space. The GASD is stored in a Coordination Namespace that is stored in a memory that is distributed amongst the nodes. A mapping that is included in the GASD is used to determine the node where the shared virtual address currently resides. The shared virtual address is then accessed from the node where it currently resides.

An approach is disclosed that locates a named data element by a local node. A name corresponding to the named data element is received, the named data element exists in a Coordination Namespace allocated in a memory area that is distributed amongst a set of nodes that include the local node and remote nodes. A predicted node identifier is received and then the named data element is requested from the predicted node based on the predicted node identifier.

A symmetrical multi-processing (SMP) node, a distributed SMP (DSMP) system comprising a plurality of SMP nodes, and a method implemented in the SMP node are disclosed. The SMP node comprises: a plurality of processors, a memory coupled to the plurality of processors, and a memory coherent proxy coupled to the plurality of processors through a coherent accelerator interface. The memory coherent proxy is configured to manage statuses of cache lines in the memory.

Methods and systems for managing storage of data in a distributed system are disclosed. To manage storage of data in a distributed system, a data processing system may include a network interface controller (NIC). The network interface controller may present emulated storages that may be used for data storage. The emulated storage devices may utilize storage resources of storage devices. The storage devices may be remote to the NIC. To reduce communication bandwidth and/or use of resources of the storage devices, the NIC and/or NICs of other data processing systems may implemented a distributed cache for data stored in the storage devices. The NICs may implement a method of managing the distributed cache to maintain synchronization between the distributed cache and the data stored in the storage devices.

A processing system includes a first set of one or more processing units including a first processing unit, a second set of one or more processing units including a second processing unit, and a memory having an address space shared by the first and second sets. The processing system further includes a distributed coherence directory subsystem having a first coherence directory to support a first subset of one or more address regions of the address space and a second coherence directory to support a second subset of one or more address regions of the address space. In some implementations, the first coherence directory is implemented in the system so as to have a lower access latency for the first set, whereas the second coherence directory is implemented in the system so as to have a lower access latency for the second set.

A heterogeneous computing system includes a first processor and a second processor that are heterogeneous. The second processor is configured to sequentially execute a plurality of kernels offloaded from the first processor. A coherency controller is configured to classify each of the plurality of kernels into one of a first group and a second group, based on attributes of instructions included in each of the plurality of kernels before the plurality of kernels are executed and is further configured to reclassify one of the plurality of kernels from the second group to the first group based on a transaction generated between the first processor and the second processor during execution of the one of the plurality of kernels.

Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

A method, apparatus, and system for prefetching exclusive cache coherence state for store instructions is disclosed. An apparatus may comprise a cache and a gather buffer coupled to the cache. The gather buffer may be configured to store a plurality of cache lines, each cache line of the plurality of cache lines associated with a store instruction. The gather buffer may be further configured to determine whether a first cache line associated with a first store instruction should be allocated in the cache. If the first cache line associated with the first store instruction is to be allocated in the cache, the gather buffer is configured to issue a pre-write request to acquire exclusive cache coherency state to the first cache line associated with the first store instruction.

Provided are a computer program product, system, and method to transfer track format information for tracks in cache at a primary storage system to a secondary storage system to which tracks are mirrored to use after a failover or failback. In response to a failover from the primary storage system to the secondary storage system, the primary storage system adds a track identifier of the track and track format information indicating a layout of data in the track, indicated in track metadata for the track in the primary storage, to a cache transfer list. The primary storage system transfers the cache transfer list to the secondary storage system to use the track format information in the cache transfer list for a track staged into the secondary cache having a track identifier in the cache transfer list.