In an embodiment, a processor may include an execution engine to execute a plurality of instructions, a memory to store a tagged data structure comprising a plurality of entries, and an eviction circuit. The eviction circuit may be to: generate a pseudo-random number responsive to an eviction request for the tagged data structure; in response to a determination that the pseudo-random number is outside of a valid eviction range for the plurality of entries, generate an alternative identifier by rotating through the valid eviction range, the valid eviction range comprising a range of numbers that are valid to identify victim entries of the tagged data structure; and evict a victim entry from the tagged data structure, the victim entry associated with the alternative identifier. Other embodiments are described and claimed.

In various embodiments, a computing system includes, for example, a plurality of processing units that share access to a system cache. A cache management application receives, for example, resource savings information for each processing unit. The resource savings information indicates, for example, amounts of a resource (e.g., power) that are saved when different units of the system cache are allocated to a processing unit. The cache management application determines, for example, the number of units of system cache to allocate to each processing unit based on the received resource savings information.

In accordance with various aspects of the invention, a recall transaction is issued if a tag filter entry needs to be freed up for an incoming transaction. Directory entries chosen for a recall transaction are pushed into a fully associative structure called victim buffer. If this structure gets full, then an entry is selected from entries inside the victim buffer for the recall.

The present disclosure relates generally to computer systems and, more particularly, to a cache refresh system and related processes and methods of use. The method of refreshing data in cache memory includes: setting, by a computer system, a refresh indicator to “true”; refreshing data in the cache memory, by the computer system, upon a determination that the refresh indicator is set to “true”; and setting, by the computer system, the refresh indicator to “false” after the refreshing of the cache memory.

A microprocessor includes a physically-indexed-and-tagged second-level set-associative cache. Each cache entry is uniquely identified by a set index and a way number. Each entry of a write-combine buffer (WCB) holds write data to be written to a write physical memory address, a portion of which is a write physical line address. Each WCB entry also holds a write physical address proxy (PAP) for the write physical line address. The write PAP specifies the set index and the way number of the cache entry into which a cache line specified by the write physical line address is allocated. In response to receiving a store instruction that is being committed and that specifies a store PAP, the WCB compares the store PAP with the write PAP of each WCB entry and requires a match as a necessary condition for merging store data of the store instruction into a WCB entry.

Examples described herein relate to a central processing unit (CPU) that includes at least two cores, at least two caching agents (CAs), and circuitry to monitor a workload mapped to a CA of the at least two CAs and adjust the workload allocated to the CA to allocation among the CA and at least one other CA of the at least two CAs based on the monitored workload.

Aspects relate to Input/Output (IO) Memory Management Units (MMUs) that include hardware structures for implementing virtualization. Some implementations allow guests to setup and maintain device IO tables within memory regions to which those guests have been given permissions by a hypervisor. Some implementations provide hardware page table walking capability within the IOMMU, while other implementations provide static tables. Such static tables may be maintained by a hypervisor on behalf of guests. Some implementations reduce a frequency of interrupts or invocation of hypervisor by allowing transactions to be setup by guests without hypervisor involvement within their assigned device IO regions. Devices may communicate with IOMMU to setup the requested memory transaction, and completion thereof may be signaled to the guest without hypervisor involvement. Various other aspects will be evident from the disclosure.

Memory system features may promote cache coherency where first and second memory clients may attempt to work on the same data. A second client cache system may provide a read request for data and associated metadata. The metadata element may be detected in a first client cache system. The first client cache system may write or flush, such as to a system memory, one or more cache lines containing the metadata and associated data and invalidate the flushed cache lines. The second client cache system may receive the data and metadata, such as from the system memory, completing or fulfilling the read request.

Methods, systems, and devices for cache metadata management in a memory subsystem are described. The memory subsystem may include an interface controller coupled with a non-volatile memory and a volatile memory. The interface controller may use metadata, such as validity information and dirty information, to operate the volatile memory as cache. The interface controller may store the dirty information in the volatile memory and may store the validity information in an array in the interface controller.

In a computer system, a processor and an I/O device controller communicate with each other via a coherence interconnect and according to a cache coherence protocol. Registers of the I/O device controllers are mapped to the cache coherent memory space to allow the processor to treat the registers as cacheable memory. As a result, latency of processor commands executed by the I/O device controller is decreased, and size of data stored in the I/O device controller that can be accessed by the processor is increased from the size of a single register to the size of an entire cache line.