Patent classifications
G06K19/07381
RFID TAG WITH ANTI-TAMPER ASSEMBLY
A radio frequency identification (RFID) transponder may include a substrate and a device. The substrate may be in communication with a controller and an antenna, and the antenna is arranged to receive radio frequency signals. A first side surface of the substrate may include a capacitor. The device may be detachably coupled with the substrate via a conductive member positioned between the structure and the capacitor of the substrate, and the conductive member may be within a desired proximity of the capacitor. The structure may be attached to an attachment surface so that an attachment strength between the structure and the attachment surface may be greater than a force required to decouple the structure from the substrate. When the structure is decoupled from the substrate, the conductive member separates from the capacitor, disabling the transponder.
Dual communication frequency RFID circuit equipped with a tamper-evident loop
A dual communication frequency RFID circuit includes a logic unit for processing data signals received or transmitted at a first frequency by a first antenna or at a second frequency by a second antenna, and a unit for managing the state of a tamper loop linked to the integrated circuit by two connection terminals. The management unit includes a first low-pass filter linked to a first connection terminal, a second low-pass filter linked to a second connection terminal, a current source for supplying a current through the first low-pass filter, a switch linked at the output of the second low-pass filter, and a first inverter connected between the current source and the first low-pass filter for supplying an output signal for the state of the tamper loop to the logic unit.
Integrated circuit chip protection against physical and/or electrical alterations
An integrated circuit chip and a method for protecting the integrated circuit chip against physical and/or electrical alterations are disclosed. The chip comprises at least one semiconductor layer including semiconductor components and conductive tracks, at least one layer formed by a first type of conductive tracks extending over all or part of a surface of the chip and at least one second type of conductive track connected to at least one detection circuit configured to detect an alteration of the at least one second type of conductive track. The chip is characterized in that the at least one first type of conductive track is mixed within the at least one second type of conductive track, the material and the layout of at least one second type of conductive track being indiscernible, by an observation device, from the material and the layout of the at least one first type of conductive track.
TAMPER-RESISTANT TRANSACTION CARD AND METHOD OF PROVIDING A TAMPER-RESISTANT TRANSACTION CARD
A dynamic transaction card that is manufactured using conductive plastic jumpers that will dissolve when in contact with a solvent used to tamper with the dynamic transaction card. Internal components of a dynamic transaction card may be manufactured using a synthetic or semi-synthetic organic material, such as, for example, plastics. These materials may be conductive to provide functionality to a dynamic transaction card, such as a connection between an integrated circuit and other card components such that when the materials dissolve, the connections are broken and the dynamic transaction card may be inactive due to the loss of various connections.
Tamper-resistant transaction card and method of providing a tamper-resistant transaction card
A dynamic transaction card that is manufactured using conductive plastic jumpers that will dissolve when in contact with a solvent used to tamper with the dynamic transaction card. Internal components of a dynamic transaction card may be manufactured using a synthetic or semi-synthetic organic material, such as, for example, plastics. These materials may be conductive to provide functionality to a dynamic transaction card, such as a connection between an integrated circuit and other card components such that when the materials dissolve, the connections are broken and the dynamic transaction card may be inactive due to the loss of various connections.
Electronic Chip Architecture
In some embodiments, an electronic chip includes a doped semiconductor substrate of a first conductivity type, and wells of the second conductivity type on the side of the front face of the chip, in and on which wells circuit elements are formed. One or more slabs of a second conductivity type are buried under the wells and are separated from the wells. The electronic chip also includes, for each buried slab, a biasable section of the second conductivity type, which extends from the front face of the substrate to the buried slab. A first MOS transistor with a channel of the first conductivity type is disposed in the upper portion of each section, where the first transistor is an element of a flip-flop. A circuit is used for detecting a change in the logic level of one of the flip-flops.
RFID tag with anti-tamper assembly
A radio frequency identification (RFID) transponder may include a substrate and a device. The substrate may be in communication with a controller and an antenna, and the antenna is arranged to receive radio frequency signals. A first side surface of the substrate may include a capacitor. The device may be detachably coupled with the substrate via a conductive member positioned between the structure and the capacitor of the substrate, and the conductive member may be within a desired proximity of the capacitor. The structure may be attached to an attachment surface so that an attachment strength between the structure and the attachment surface may be greater than a force required to decouple the structure from the substrate. When the structure is decoupled from the substrate, the conductive member separates from the capacitor, disabling the transponder.
Anti-skimming payment card
A payment card may include a read sensor configured to detect a reading of the payment card by a card reader. In particular, the payment card may include a controller or a processor configured to count a number of times the payment card is read by other card readers. The payment card may implement card security measures based on the number of reads detected by the read sensor. The payment card may further include a magnetic stripe emulator configured to emulate signal patterns of a magnetic stripe when the magnetic stripe is read by a card reader. The controller may disable the magnetic stripe emulator when the number of reads detected by the read sensor exceeds a predetermined number.
SYSTEM AND METHODS FOR SECURE FIRMWARE VALIDATION
An electronic device, such as a dynamic transaction card having an EMV chip, that acts as a TPM having a memory, an applet, and a cryptographic coprocessor performs secure firmware and/or software updates, and performs firmware and/or software validation for firmware and/or software that is stored on the electronic device. Validation may compare a calculated checksum with a checksum stored in EMV chip memory. If a checksum calculated for firmware and/or a software application matches a checksum stored in EMV chip memory of the transaction card, the transaction card may operate normally. If a checksum calculated for firmware and/or a software application does not match a checksum stored in EMV chip memory of the transaction card, the transaction card may freeze all capabilities, erase the memory of the transaction card, display data indicative of a fraudulent or inactive transaction card, and/or the like.
Protected integrated circuit
The integrated circuit includes a functional block performing a logic and/or analog function. A control circuit is configured to transmit at least a first signal to the receiver and receive a second signal from receiver. The electrically conducting lines' first and second series connect the control circuit and receiver to perform the first and second signals' transit. A plurality of monitoring stations is simultaneously connected to first and second series of electrically conducting lines to define a first elementary electric pattern in the electrically conducting lines' first series and a distinct second elementary electric pattern equivalent to first elementary electric pattern in the electrically conducting lines' second series. A shield at least partially covers the functional block. The control circuit is configured to detect modification of first elementary electric pattern with respect to the second elementary electric pattern by absence of receipt of the second signal after a predefined time-out.