Disclosed is a display device including a first output part, a second output part, a power supply circuit connected to input terminals of the first output part and the second output part, a first sensing part connected to an output terminal of the first output part, a second sensing part connected to an output terminal of the second output part, a first voltage output terminal connected to the first sensing part and the second sensing part, a plurality of pixels connected to the first voltage output terminal and configured to display an image, and a defect determination part controlling shutdown of the power supply circuit by comparing a first sensing value and a second sensing value, which are received from the first sensing part and the second sensing part, with a first reference value and a second reference value having a level lower than the first reference value.

A buck-boost power converter is operable in a first mode (step-down) or in a second mode (step-up). The power converter has an inductor, a flying capacitor, a network of six switches and a driver adapted to drive the network of switches with a sequence of states. Depending on the mode of operation the sequence of states comprises at least one of a first state and a second state. In the first state the ground port is coupled to the second port via two paths, a first path comprising the flying capacitor and the inductor, and a second path comprising the flying capacitor while bypassing the inductor. In the second state the first port is coupled to the second port via a path that includes the inductor and the ground port is coupled to the first port via a path that includes the flying capacitor while bypassing the inductor.

A buck-boost power converter is operable in a first mode (step-down) or in a second mode (step-up). The power converter has an inductor, a flying capacitor, a network of six switches and a driver adapted to drive the network of switches with a sequence of states. Depending on the mode of operation the sequence of states comprises at least one of a first state and a second state. In the first state the ground port is coupled to the second port via two paths, a first path comprising the flying capacitor and the inductor, and a second path comprising the flying capacitor while bypassing the inductor. In the second state the first port is coupled to the second port via a path that includes the inductor and the ground port is coupled to the first port via a path that includes the flying capacitor while bypassing the inductor.

A display device includes: a display area and a non-display area; a first pixel area and a second pixel area, each provided in the display area; scan lines extending in a first direction and disposed in the first pixel area and the second pixel area; first sub-scan lines extending in a second direction and disposed in the first pixel area, the second direction intersecting the first direction; second sub-scan lines extending in the second direction and disposed in the first pixel area and the second pixel area; and a pad part provided in the non-display area, the pad part being electrically connected to the first sub-scan lines and the second sub-scan lines. The scan lines are electrically connected to at least one of the first sub-scan lines and the second sub-scan lines. The first sub-scan lines do not overlap the second pixel area in a plan view.

A display device including a display area and a non-display area, an inorganic insulating layer disposed on a substrate, the inorganic insulating layer disposed in the display area and the non-display area, pixels disposed on the substrate and overlapping the inorganic insulating layer in a plan view, the pixels disposed in the display area, and an organic insulating layer disposed on the substrate and overlapping the inorganic insulating layer and the pixels in a plan view, the organic insulating layer disposed at least in the display area. The non-display area includes an organic layer-free area including at least one of a corner and an outer edge area of the display device. The organic insulating layer is disposed on a portion of the substrate so as to be disposed in an area except for the organic layer-free area.

This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.

This document describes systems and techniques for image retention mitigation via voltage biasing for organic light-emitting diode (OLED) displays. In aspects, a pixel array is described having pixel circuits including a first transistor configured to receive a biasing signal from one or more drivers and, based on the biasing signal, enable or disable an application of a bias voltage at a terminal of a second transistor. In so doing, the bias voltage reduces a hysteresis effect experienced by the second transistor for each of the multiple pixel circuits of the pixel array, thereby mitigating an image retention.

A pixel circuit and a display device including the same are disclosed. The pixel circuit of this disclosure includes a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a gate electrode connected to a second node, and a second electrode connected to a third node, and configured to supply an electric current to a light emitting element; a first switch element configured to be turned on according to a gate-on voltage of a scan pulse to supply a data voltage to the second node; and a second switch element configured to be turned off according to a gate-off voltage of a light emitting control pulse generated in antiphase of the scan pulse.

A pixel circuit and a display panel including the same are disclosed. The pixel circuit may include a driving element including a gate connected to a first node to which a data voltage is configured to be applied, a first electrode connected to a high-potential voltage line, and a second electrode connected to a second node; a first switch element connected between the second node and a third node; a second switch element connected between the second node and a fourth node; a third switch element connected between the fourth node and a reference voltage line; a first capacitor connected between the first node and the third node; and a second capacitor connected between the third node and the fourth node.

A pixel circuit and a display device including the pixel circuit are disclosed. The pixel circuit according to embodiments includes a first pixel circuit connected in parallel to an initialization voltage line to which an initialization voltage is applied, and including a first-first switch element connected to a first-first gate line and a first-second switch element connected to a first-second gate line; and a second pixel circuit connected in parallel to the initialization voltage line, and including a second-first switch element connected to a second-first gate line and a second-second switch element connected to a second-second gate line, and the first-second gate line and the second-first gate line are electrically connected.