A display device includes a base layer including an active area and a peripheral area outside the active area, a circuit element layer including a pixel circuit in the active area and a driving voltage wiring located in the peripheral area to supply a driving voltage to the pixel circuit. A light emitting element layer including a plurality of light emitting elements on the circuit element layer, a thin film sealing layer to cover the light emitting element layer, and an input sensing layer on the thin film sealing layer and including a sensing electrode and a sensing signal wiring part connected to the sensing electrode. The circuit element layer includes a connection wiring part overlapping the driving voltage wiring in the peripheral area and contacts the sensing signal wiring part. The connection wiring part is at a different layer from the driving voltage wiring.

A display device includes a base layer including an active area and a peripheral area outside the active area, a circuit element layer including a pixel circuit in the active area and a driving voltage wiring located in the peripheral area to supply a driving voltage to the pixel circuit. A light emitting element layer including a plurality of light emitting elements on the circuit element layer, a thin film sealing layer to cover the light emitting element layer, and an input sensing layer on the thin film sealing layer and including a sensing electrode and a sensing signal wiring part connected to the sensing electrode. The circuit element layer includes a connection wiring part overlapping the driving voltage wiring in the peripheral area and contacts the sensing signal wiring part. The connection wiring part is at a different layer from the driving voltage wiring.

A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

A display pixel is provided that is operable to support hybrid compensation scheme having both in-pixel threshold voltage canceling and external threshold voltage compensation. The display may include multiple p-type silicon transistors with at least one n-type semiconducting-oxide transistor and one storage capacitor. An on-bias stress phase may be performed prior to a threshold voltage sampling and data programming phase to mitigate hysteresis and improve first frame response. In low refresh rate displays, a first additional on-bias stress operation can be performed separate from the threshold voltage sampling and data programming phase during a refresh frame and a second additional on-bias stress operation can be performed during a vertical blanking frame. The display pixel may be configured to receive an initialization voltage and an anode reset voltage, either of which can be dynamically tuned to match the stress of the first and second additional on-bias stress operations to minimize flicker.

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

Provided is a scan driving circuit including a plurality of unit scan driving circuits, at least one of the plurality of unit scan driving circuits including: a first transistor configured to receive a prior scan signal in synchronization with a first clock signal and to respond to an enable level of the prior scan signal to output a second clock signal as a corresponding scan signal during one cycle of the first clock signal; a second transistor coupled between the first transistor and a first voltage; and a third transistor coupled to a gate of the second transistor and configured to be turned on by a first signal. A width of a first wire configured to transfer the first clock signal and a width of a second wire configured to transfer the second clock signal are larger than that of a third wire configured to transfer the first signal.

A display device includes a display panel including a gate line, a data line, and a pixel at a crossing region of the gate line and the data line, a timing controller configured to generate a gate driving control signal, a data driving control signal, and a power control signal based on a display period corresponding to a time interval of frames, a gate driver configured to provide a gate signal to the pixel through the gate line based on the gate driving control signal, a data driver configured to provide a data signal to the pixel through the data line based on the data driving control signal, and a power supply configured to generate a power voltage to drive the pixel, and configured to adjust the power voltage based on the power control signal during the display period.

A display device includes a display panel including a gate line, a data line, and a pixel at a crossing region of the gate line and the data line, a timing controller configured to generate a gate driving control signal, a data driving control signal, and a power control signal based on a display period corresponding to a time interval of frames, a gate driver configured to provide a gate signal to the pixel through the gate line based on the gate driving control signal, a data driver configured to provide a data signal to the pixel through the data line based on the data driving control signal, and a power supply configured to generate a power voltage to drive the pixel, and configured to adjust the power voltage based on the power control signal during the display period.

A display device may include a first pixel coupled to an emission control line, and an emission control stage for selectively coupling the emission control line to a first or second supply voltage line. The emission control stage may include: a first emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the emission control line, and a main gate electrode coupled to a first node; a second emission control transistor including a first electrode coupled to the emission control line, a second electrode coupled to the second supply voltage line, and a main gate electrode coupled to a second node; and a third emission control transistor including a first electrode coupled to the first supply voltage line, a second electrode coupled to the first node, a main gate electrode coupled to the second node, and a sub-gate electrode.

A stage circuit including: an output circuit for supplying a voltage of a first or second power supply to an output terminal in response to voltages of first and second nodes; an input circuit for controlling voltages of the second node and a third node; a first signal processor for controlling the voltage of the first node; a second signal processor configured to control the voltage of the first node in response to an output voltage of a third signal processor and a signal supplied to a third input terminal; and the third signal processor for controlling the voltage of the second node. The third signal processor includes: a third capacitor coupled between the first power supply and the second node; and a third transistor coupled between the first power supply and the third input terminal, and including a gate electrode coupled to the second node.