In a display device having an external compensation function, a decrease in compensation accuracy caused by coupling noise generated in a data signal line is prevented. An emission driver that applies a light-emission control signal (EM) to each of a plurality of light-emission control lines includes a shift register formed of a plurality of unit circuits. The shift register generates a light-emission control signal (EM) to be applied to each light-emission control line on the basis of a plurality of light-emission control clock signals (ECK1 to ECK4) outputted from a display control circuit. The display control circuit stops the outputs of the plurality of light-emission control clock signals (ECK1 to ECK4) throughout a current measurement period in which a current corresponding to the characteristic of the drive transistor is measured.

A first capacitance element provided corresponding to a bit D0, a second capacitance element provided corresponding to a bit D1, and a third capacitance element and a fourth capacitance element provided corresponding to a bit D2, and electrically coupled in parallel are included. An area S1 where electrodes of the first capacitance element overlap in plan view is smaller than half an area S2 where electrodes of the second capacitance element overlap in plan view, an area in which electrodes of the third capacitance element overlap in plan view is substantially the same as the area S2, and an area where electrodes of the fourth capacitance element overlap in plan view is substantially the same as the area S2.

An electronic device is provided. The electronic device includes a driver, a driving circuit and an electronic element. The driver converts a first PWM data to a second PWM data according to a gamma setting curve, and converts a first PAM data to a second PAM data according to the gamma setting curve. The driving circuit includes a PWM circuit and a PAM circuit. The PWM circuit receives the second PWM data. The PAM circuit receives the second PAM data. The electronic element emits a light according to a driving current provided from the driving circuit.

A display apparatus that prevents visual recognition of flickering in each of display areas having different resolutions includes a first pixel circuit, a first display element, a second pixel circuit, and a second display element. The first pixel circuit includes: a first driving transistor configured to control a first current that flows to the first display element; and a first initializing transistor configured to apply a first initializing voltage to a gate of the first driving transistor in response to a first scan signal. The second pixel circuit includes: a second driving transistor configured to control a second current that flows to the second display element; and a second initializing transistor configured to apply a second initializing voltage having a level different from a level of the first initializing voltage to a gate of the second driving transistor in response to the first scan signal.

A display device which exhibits light with high color purity is provided. A display device with low power consumption is provided. An embodiment is a display device which includes a first pixel electrode, a second pixel electrode, a light-emitting layer, a common electrode, a first protective layer, and a semi-transmissive layer. The light-emitting layer includes a first region positioned over the first pixel electrode and a second region positioned over the second pixel electrode. The common electrode is positioned over the light-emitting layer. The first protective layer is positioned over the common electrode. The semi-transmissive layer is positioned over the first protective layer. Reflectivity with respect to visible light of the semi-transmissive layer is higher than reflectivity with respect to visible light of the common electrode. The semi-transmissive layer does not overlap with the first region and overlaps with the second region. For example, the semi-transmissive layer may include an opening in a position overlapping with the first region.

In a pixel circuit of a display device in which display luminance is controlled by a holding voltage of the capacitor Cst, a gate terminal of a drive transistor M1 is connected to a source terminal of the drive transistor M1 via a capacitance selection transistor M3 and the holding capacitor Cst and is also connected to the source terminal via only an auxiliary writing capacitor Cwa. During a data writing period Tw, the capacitance selection transistor M3 is turned off, and data voltage is provided from a data signal line Dj to the auxiliary writing capacitor Cwa via a writing control transistor M2. Thereafter, the writing control transistor M2 is turned off, the capacitance selection transistor M3 is turned on, so that charges are redistributed between the auxiliary writing capacitor Cwa and the holding capacitor Cst, whereby a driving holding voltage is determined.

In a pixel circuit of a display device in which display luminance is controlled by a holding voltage of the capacitor Cst, a gate terminal of a drive transistor M1 is connected to a source terminal of the drive transistor M1 via a capacitance selection transistor M3 and the holding capacitor Cst and is also connected to the source terminal via only an auxiliary writing capacitor Cwa. During a data writing period Tw, the capacitance selection transistor M3 is turned off, and data voltage is provided from a data signal line Dj to the auxiliary writing capacitor Cwa via a writing control transistor M2. Thereafter, the writing control transistor M2 is turned off, the capacitance selection transistor M3 is turned on, so that charges are redistributed between the auxiliary writing capacitor Cwa and the holding capacitor Cst, whereby a driving holding voltage is determined.

The present disclosure relates to a display device including first pixels disposed in a first pixel area, and connected to first scan lines; second pixels disposed in a second pixel area, and connected to second scan lines; a timing controller configured to supply a first clock signal and a second clock signal to a first clock line and a second clock line, respectively; a first scan driver configured to receive the first clock signal through the first clock line, and to supply a first scan signal to the first scan lines; and a second scan driver configured to receive the second clock signal through the second clock line, and to supply a second scan signal to the second scan lines, wherein the second pixel area has a smaller width than the first pixel area.

The present disclosure relates to a display device including first pixels disposed in a first pixel area, and connected to first scan lines; second pixels disposed in a second pixel area, and connected to second scan lines; a timing controller configured to supply a first clock signal and a second clock signal to a first clock line and a second clock line, respectively; a first scan driver configured to receive the first clock signal through the first clock line, and to supply a first scan signal to the first scan lines; and a second scan driver configured to receive the second clock signal through the second clock line, and to supply a second scan signal to the second scan lines, wherein the second pixel area has a smaller width than the first pixel area.

A light emission driving circuit includes a driving circuit configured to output a light emission driving signal to a first output terminal and output a switching signal to a first node in response to clock signals and a first carry signal, and a first masking circuit configured to output a second carry signal to a second output terminal in response to a masking clock signal, the light emission driving signal, and the first switching signal. The masking clock signal is a signal which is maintained at a first level during a normal mode and periodically changes during a low power mode.