A display device includes a first substrate including an active area, a bending area, and a pad area; a plurality of pixels to display an image in the active area, each of the plurality of pixels including an organic light emitting diode (OLED); a signal line and a power line disposed on the first substrate, the signal line and the power ling being disposed on a same layer in the bending area, the bending area on the first substrate being configured to be bent flexibly; and a second substrate facing the active area and disposed on the first substrate.

A display driver includes an image processing circuit and a driver circuit. The image processing circuit is configured to: receive input image data corresponding to an input image; generate first subpixel rendered data from a first part of the input image data for a first display region of a display panel using a first setting; and generate second subpixel rendered data from a second part of the input image data for a second display region of the display panel using a second setting different from the first setting. The first pixel layout is different than the second pixel layout. The driver circuit is configured to update the first display region of the display panel based at least in part on the first subpixel rendered data and update the second display region of the display panel based at least in part on the second subpixel rendered data.

A display device includes: a plurality of pixels each including a driving thin film transistor and a storage capacitor, wherein each of the pixels further includes: a driving semiconductor layer including a driving channel region, a driving source region, and a driving drain region; a first electrode layer, a portion of the first electrode layer overlapping the driving channel region; a second electrode layer overlapping the first electrode layer; a node connection line having a first side connected to the first electrode layer; a pixel electrode overlapping the first electrode layer and the second electrode layer; and a shielding layer between the first electrode layer and the pixel electrode and overlapping the first electrode layer, the node connection line, and the pixel electrode.

A display device includes: a plurality of pixels each including a driving thin film transistor and a storage capacitor, wherein each of the pixels further includes: a driving semiconductor layer including a driving channel region, a driving source region, and a driving drain region; a first electrode layer, a portion of the first electrode layer overlapping the driving channel region; a second electrode layer overlapping the first electrode layer; a node connection line having a first side connected to the first electrode layer; a pixel electrode overlapping the first electrode layer and the second electrode layer; and a shielding layer between the first electrode layer and the pixel electrode and overlapping the first electrode layer, the node connection line, and the pixel electrode.

A gamma measurement method of a display device includes: storing a current value that is measured during gamma tuning of a display panel; resetting a target current of global current management (GCM) by referring to the current value; and measuring gamma of the display panel while applying the target current of the GCM.

A gamma measurement method of a display device includes: storing a current value that is measured during gamma tuning of a display panel; resetting a target current of global current management (GCM) by referring to the current value; and measuring gamma of the display panel while applying the target current of the GCM.

The present application discloses an organic light-emitting display panel and a driving method thereof, as well as an organic light-emitting display device. The display panel includes: an array arrangement including pixel units, wherein each pixel unit comprises a first, a second, a third and a fourth subpixels; a pixel circuit is formed in each subpixel; the first, second, third and fourth subpixels of an identical pixel unit are arranged along a column direction and are electrically connected with a given reference signal line; a color of the first subpixel, a color of the second subpixel, a color of the third subpixel and a color of the fourth subpixel differ from one another, and the color of the first subpixel, the color the second subpixel and the color the third subpixel are red, blue and green, respectively; and the color of the fourth subpixel is not white.

A display device includes at least a first luminance range and a second luminance range which includes a luminance different from the first luminance range. In a boundary area of a second dimming range corresponding to the second luminance range and which is adjacent to a first dimming range corresponding to the first luminance range, a reference luminance emitted from a pixel is maintained as a first constant luminance value, and an off-duty number, which is the number of periods in which the pixel is turned off during one frame, is gradually increased by an emission control signal.

A display device includes at least a first luminance range and a second luminance range which includes a luminance different from the first luminance range. In a boundary area of a second dimming range corresponding to the second luminance range and which is adjacent to a first dimming range corresponding to the first luminance range, a reference luminance emitted from a pixel is maintained as a first constant luminance value, and an off-duty number, which is the number of periods in which the pixel is turned off during one frame, is gradually increased by an emission control signal.

A pixel circuit including an organic light emitting diode, a first transistor configured to drive the organic light emitting diode, a second transistor electrically connected between a gate node of the first transistor and a data line, a third transistor electrically connected between a source node of the first transistor and an initialization voltage line and a storage capacitor electrically connected between the gate node and the source node of the first transistor. In a data writing period in which the storage capacitor is charged with electric charges, a turn-off time of the third transistor lags compared to a turn-off time of the second transistor.