The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

A bit line structure for two-transistor static random access memory (2T SRAM), including multiple bit lines extending over multiple 2T SRAMs in a first direction, wherein each bit line consists of multiple first portions and second portions extending in the first direction and electrically connecting with each other in an alternating manner, and the first portions and the second portions are in a first dielectric layer and a second dielectric layer respectively, and the first portions of each bit line correspond to the second portions of adjacent bit lines.

A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive an access line of the memory array to a discharging voltage during an IDLE phase, to drive said access line to a floating voltage during an ACTIVE phase, and to drive said access line at least to a first or second read/program voltage during a PULSE phase.

A first value is stored in a first memory cell. A first component output current, from a first electronic component, is provided based on the stored first value, wherein the first component output current is proportional to a place value represented by the first value. A second value is stored in a second memory cell. A second component output current, from a second electronic component, is provided based on the stored second value, wherein the second component output current is proportional to a place value represented by the second value. A combined current of at least the first component output current and the second component output current is detected, wherein the combined current corresponds to a sum of at least the first value and the second value.

A memory device comprises a first selector and a storage capacitor in series with the first selector. A second selector is in parallel with the storage capacitor coupled between the first selector and zero volts. A plurality of memory devices form a 2S-1C cross-point DRAM array with 4F2 or less density.

Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming. A method is provided for multiple-page programming of an array having a block that includes page groups and each page group includes cell strings that form pages. The method includes deactivating drain select gates (DSGs) and source select gates (SSG), applying a programming voltage to a selected word line, and applying a middle high voltage to unselected word lines. The method also includes repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation. Each programming operation includes loading data onto bit lines and pulsing a drain select gate associated with a selected page group to load the data into a selected page of the selected page group.

A counter can have a number of sensing components. Each respective sensing component can be configured to sense a respective event and can include a respective first capacitor configured to be selectively coupled to a second capacitor in response to the respective sensing component sensing the respective event. The second capacitor can be configured to be charged to a voltage by each respective first capacitor that is selectively coupled to the second capacitor. The counter can have a comparator with a first input coupled to the second capacitor and a second input coupled to a reference voltage corresponding to a threshold quantity of events. The comparator can be configured to output a signal indicative of the threshold quantity of events being sensed in response to the voltage of the second capacitor being greater than or equal to the reference voltage.