The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a memory array including a plurality of memory cells, each memory cell having an impedance that varies in accordance with a respective data value stored therein; and a tracking memory cell having an impedance based on a tracking data value stored therein; and a read circuit coupled to the memory array, the read circuit configured to determine an impedance of a selected memory cells with respect to the impedance of the tracking memory cell; read a data value stored within the selected memory cell based upon a voltage change of a signal node voltage corresponding to the impedance of the selected memory cell.

The present disclosure describes a memory device comprising memory cells at cross points of access lines of a memory array, and a two-transistor driver comprising a P-type transistor and a N-type transistor connected to the P-type transistor, the two-transistor driver being configured to drive an access line of the memory array to a discharging voltage during an IDLE phase, to drive said access line to a floating voltage during an ACTIVE phase, and to drive said access line at least to a first or second read/program voltage during a PULSE phase.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

Methods and apparatus for writing nonvolatile 3D NAND flash memory using multiple-page programming. A method is provided for multiple-page programming of an array having a block that includes page groups and each page group includes cell strings that form pages. The method includes deactivating drain select gates (DSGs) and source select gates (SSG), applying a programming voltage to a selected word line, and applying a middle high voltage to unselected word lines. The method also includes repeating multiple programming operations while maintaining the word line voltage levels from a first programming operation to a last programming operation. Each programming operation includes loading data onto bit lines and pulsing a drain select gate associated with a selected page group to load the data into a selected page of the selected page group.

Methods, devices, and systems are disclosed that generally perform a time delay determination of a voltage change on a signal node to determine a corresponding signal value on another node causing the voltage change. In an example the circuit device includes a first circuit configured to couple, when enabled, a signal value onto a first node, and a read circuit having an input coupled to the first node. The read circuit is configured to effect a voltage transition of a signal node at a variable rate corresponding to the voltage of the first node, and to determine the signal value based upon a time-to-transition measurement of the signal node.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

The present disclosure relates to circuits, systems, and methods of operation for a memory device. In an example, a memory device includes a plurality of memory cells, each memory cell having a variable impedance that varies in accordance with a respective data value stored therein; and a read circuit configured to read the data value stored within a selected memory cell based upon a variable time delay determination of a signal node voltage change corresponding to the variable impedance of the selected memory cell.

A memory circuit including: memory cells, each including a storage cell transistor; a first tracking bit line; and a tracking circuit, electrically coupled between a first tracking word line and a reference voltage node, including a first set of first tracking cells, each first tracking cell including a first cell transistor having a same transistor configuration as each storage cell transistor; and wherein: a driving capacity of the storage cell transistors of the memory cells has a storage cell statistical distribution that exhibits a weak bit current value; a driving capacity of the first cell transistors of the first set of tracking cells has a first tracking cell statistical distribution that exhibits a first strong bit current value; and a first quantity of the first tracking cells is sufficient to cause the first strong bit current value to be equal to or less than the weak bit current value.