According to one embodiment, a semiconductor memory device includes a memory cell, a sense amplifier, a first transfer transistor, a second transfer transistor, and a controller. The memory cell can store a first value and a second value. The sense amplifier amplifies the first value or the second value read from the memory cell to the sense node. The first transfer transistor has a first control terminal connected to the sense node. The second transfer transistor has a second control terminal connected to the sense node. The controller applies a backgate potential to backgate terminals of the first transfer transistor and the second transfer transistor.

An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

A semiconductor device for efficiently compressing a large volume of image data is provided. The semiconductor device includes a memory cell array, an analog processing circuit, a writing circuit, and a row driver, whereby highly efficient compressing of image data can be performed. A first current corresponding to first data and a second current corresponding to one of a plurality of second data that is a target for comparison with the first data are generated in the writing circuit. A differential current between the first current and the second current is supplied to the analog processing circuit, so that the first data and the plurality of second data are compared. Accordingly, a piece of the second data that has the same content as the first data is detected, and a displacement from the first data to the second data can be calculated.

An electrical circuit is disclosed that comprises plurality of tunneling field-effect transistors (TFETs) arranged in a diffusion network matrix having a plurality of nodes wherein, for each of the TFETs that is not on an end of the matrix, a drain of the TFET is electrically coupled with the source of at least one of the other TFETs at a node of the matrix and a source of the TFET is electrically coupled with the drain of at least one of the other TFETs at another node of the matrix. The electrical circuit further comprises a plurality of capacitors, wherein a respective one of the plurality of capacitors is electrically coupled with each node that includes the source of at least one TFET and the drain of at least one TFET. The TFETs may be symmetrical graphene-insulator-graphene field-effect transistors (SymFETs), for example.

A semiconductor device for efficiently compressing a large volume of image data is provided. The semiconductor device includes a memory cell array, an analog processing circuit, a writing circuit, and a row driver, whereby highly efficient compressing of image data can be performed. A first current corresponding to first data and a second current corresponding to one of a plurality of second data that is a target for comparison with the first data are generated in the writing circuit. A differential current between the first current and the second current is supplied to the analog processing circuit, so that the first data and the plurality of second data are compared. Accordingly, a piece of the second data that has the same content as the first data is detected, and a displacement from the first data to the second data can be calculated.

An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

An in-memory computing (IMC) memory device comprises a plurality of computing memory cells and a plurality of balance computing memory cells forming a plurality of memory strings. In programming, a first resistance state number of the balance computing memory cells is determined based on a first resistance state number of the computing memory cells of the memory string. In IMC operations, when a read voltage is applied to the computing memory cells, the computing memory cells generate a plurality of cell currents which are summed into a plurality of memory string currents; the memory string currents charge a loading capacitor; a capacitor voltage of the loading capacitor is measured; and based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the input values and the weight values is determined.

A memory device comprising a plurality of first global access lines, second global access lines, first local access lines, and second local access lines; and a plurality of memory cells, wherein a memory cell is coupled to one of the first local access lines and one of the second local access lines. The memory device further comprises a plurality of signal lines to communicate local access line select signals to control a plurality of select devices, wherein a select device selectively couples one of the first global access lines to one of the first local access lines; and a NOR gate to accept the plurality of local access line select signals as inputs and generate a plurality of local access line deselect signals to control a plurality of deselect devices, wherein a deselect device selectively couples one of the first local access lines to a deselect voltage.

Multi-stage charge pumps use a modular structure in which each stage include a pair of legs, or current paths, between the stage input and the stage output. Each leg includes a stage boosting capacitor having a first plate connected to the current path and a second plate connected to receive one of a pair of non-overlapping clock signals. Each leg has an NMOS charge transfer switch connected between the stage input and the first plate of the stage boosting capacitor and a PMOS charge transfer switch connected between the first plate of the stage boosting capacitor and the stage output. To reduce charge pump area, the NMOS and PMOS charge transfer switches are formed to have a same resistance value when in an on state, where to achieve this the NMOS charge transfer switches are formed with wider control gates than the PMOS charge transfer switches.

A memory array circuit includes a semiconductor substrate, a bit line, a complementary bit line, and a bit line sense amplifier circuit. The semiconductor substrate has an original surface. The bit line sense amplifier circuit is connected to the bit line and the complementary bit line, and the bit line sense amplifier circuit includes a first plurality of transistors and a first set of connection lines. Each transistor includes a gate node, a first conductive node, and a second conductive node. The first set of connection lines connects the first plurality of transistors to the bit line and the complementary bit line; wherein the first set of connection lines is above the original surface of the semiconductor substrate, and the bit line and the complementary bit line are under the original surface of the semiconductor substrate.