A memory component includes a memory core comprising dynamic random access memory (DRAM) storage cells and a first circuit to receive external commands. The external commands include a read command that specifies transmitting data accessed from the memory core. The memory component also includes a second circuit to transmit data onto an external bus in response to a read command and pattern register circuitry operable during calibration to provide at least a first data pattern and a second data pattern. During the calibration, a selected one of the first data pattern and the second data pattern is transmitted by the second circuit onto the external bus in response to a read command received during the calibration. Further, at least one of the first and second data patterns is written to the pattern register circuitry in response to a write command received during the calibration.

A control circuit includes a bias circuit. The bias circuit is configured to provide a bias current for a functional circuit. The bias circuit includes a first bias circuit and a second bias circuit. The first bias circuit is configured to provide a first bias current, and the second bias circuit is configured to provide a second bias current. Herein, the first bias current is smaller than the second bias current, the first bias circuit is configured to be in a normally open state after being powered on, and the second bias circuit is configured to receive a bias enabling signal and provide the second bias current based on the bias enabling signal.

A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.

Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

Provided are a memory detection method, a computer device and a storage medium. The method includes: initializing all storage units in a storage unit array; determining a plurality of target wordlines, two adjacent target wordlines being provided with a plurality of interfering wordlines therebetween; turning on the target wordlines, and performing a write operation on storage units connected to the target wordlines; performing repeatedly turn-on and turn-off of the interfering wordlines for a plurality of times; and performing a read operation on the storage units connected to the target wordlines. A write operation is performed on the storage units connected to the interfering wordlines by means of forced current sinking.

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a readout circuit layout, including: a first PMOS layout, configured to form a first PMOS transistor <P1>, wherein a source of the first PMOS transistor is connected to a first signal terminal, and the first signal terminal is configured to receive a first level signal; a first NMOS layout, configured to form a first NMOS transistor <N1>, wherein a source of the first NMOS transistor is connected to a second signal terminal, and the second signal terminal is configured to receive a second level signal; a gate of the first PMOS transistor <P1> and a gate of the first NMOS transistor <N1> are connected to a bit line, and a drain of the first PMOS transistor <P1> and a drain of the first NMOS transistor <N1> are connected to a complementary readout bit line.

The present disclosure relates to the field of semiconductor circuit design, and in particular, to a readout circuit layout, including: a first PMOS layout, configured to form a first PMOS transistor <P1>, wherein a source of the first PMOS transistor is connected to a first signal terminal, and the first signal terminal is configured to receive a first level signal; a first NMOS layout, configured to form a first NMOS transistor <N1>, wherein a source of the first NMOS transistor is connected to a second signal terminal, and the second signal terminal is configured to receive a second level signal; a gate of the first PMOS transistor <P1> and a gate of the first NMOS transistor <N1> are connected to a bit line, and a drain of the first PMOS transistor <P1> and a drain of the first NMOS transistor <N1> are connected to a complementary readout bit line.

The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

The present disclosure provides a method for detecting a memory and a device for detecting a memory. The memory includes first memory cells, second memory cells, bit lines, complementary bit lines, word lines, and a plurality of sense amplifiers, where each of the sense amplifiers is electrically coupled to a bit line and a complementary bit line; and the method includes: writing storage data into each of the first memory cells and each of the second memory cells; performing a read operation; obtaining a test result based on a difference between real data and the storage data; and obtaining a leakage position of the bit line and the word line or a leakage position the complementary bit line and the word line based on the test result.

A computer device, a setting method for a memory module, and a mainboard are provided. The computer device includes a memory module, a processor, and the mainboard. A basic input output system (BIOS) of the mainboard stores an extreme memory profile (XMP). When the processor performs the BIOS so that the computer device displays a user interface (UI), the BIOS displays an overclocking option corresponding to the XMP in a selection list of the UI. When the BIOS receives a selection request corresponding to the overclocking option of the selection list, the BIOS reads multiple memory setting parameters corresponding to the XMP, and configures the memory module according to the memory setting parameters.